Frequency stabilization

Patent metadata

Field	Value
Publication number	US-11496138-B2
Application number	US-202117365783-A
Country	US
Kind code	B2
Filing date	Jul 1, 2021
Priority date	Jul 2, 2020
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.

First claim

What is claimed is:

1. An apparatus comprising:
a first supply voltage node;
a second supply voltage node;
an oscillator circuit coupled to the first supply voltage node and configured to generate a clock signal;
at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, the at least one clock buffer configured to selectively be in:
a disabled state; or
an enabled state to pass the clock signal to at least one client of multiple clients; and

at least one load circuit comprising:
an input coupled to the output of the oscillator circuit; and
an output configured to be coupled to a ground, the at least one load circuit configured to:
be connected to the first supply voltage node for at least a portion of time; and
controllably adjust a magnitude of a supply voltage provided by the first supply voltage node.

2. The apparatus of claim 1 , wherein the at least one load circuit is configured to adjust the magnitude of the supply voltage between approximately 1 and 10 millivolts.

3. The apparatus of claim 1 , wherein:
the at least one load circuit is configured to be disconnected from the multiple clients configured to receive the clock signal or a signal based on the clock signal; and
the at least one load circuit is not directly connected to the multiple clients.

4. The apparatus of claim 1 , wherein the at least one load circuit is configured to:
be disconnected from the multiple clients configured to receive the clock signal or a signal based on the clock signal; and
selectively be in:
the disabled state; or
the enabled state to adjust the supply voltage of the first supply voltage node.

5. The apparatus of claim 1 , wherein the at least one clock buffer and the at least one load circuit are configured to selectively be in the disabled state or the enabled state together.

6. The apparatus of claim 1 , wherein:
the at least one clock buffer comprises a first clock buffer;
the at least one load circuit comprises a second clock buffer; and
the apparatus further comprises a switch circuit configured to selectively:
connect the second clock buffer to the first supply voltage node and disconnect an output of the second clock buffer from an output node; or
connect the second clock buffer to the second supply voltage node and connect the output of the second clock buffer to the output node.

7. The apparatus of claim 6 , wherein the switch circuit comprises:
a first switch coupled between the second clock buffer, the first supply voltage node, and the second supply voltage node; and
a second switch coupled between the output of the second clock buffer and the output node.

8. The apparatus of claim 1 , wherein the at least one load circuit comprises:
at least one buffer having an input coupled to the output of the oscillator circuit;
at least one capacitor coupled between an output of the at least one buffer and the ground; and
at least one frequency divider circuit coupled between the output of the oscillator circuit and the input of the at least one buffer.

9. The apparatus of claim 1 , wherein:
the at least one load circuit comprises:
at least one buffer having an input coupled to the output of the oscillator circuit; and
at least one capacitor coupled between an output of the at least one buffer and the ground;

the at least one buffer comprises multiple buffers implemented in parallel; and
the at least one load circuit is configured to enable different portions of the multiple buffers to adjust the supply voltage of the first supply voltage node by different amounts.

10. The apparatus of claim 1 , wherein:
the at least one load circuit comprises:
at least one buffer having an input coupled to the output of the oscillator circuit; and
at least one capacitor coupled between an output of the at least one buffer and the ground;

the at least one capacitor comprises a trimming capacitor having a variable capacitance; and
the at least one load circuit is configured to adjust the variable capacitance of the trimming capacitor to adjust the supply voltage of the first supply voltage node by different amounts.

11. The apparatus of claim 1 , wherein the oscillator circuit comprises a single resonator.

12. The apparatus of claim 11 , wherein the single resonator comprises a quartz crystal.

13. The apparatus of claim 1 , further comprising:
an integrated circuit, the integrated circuit comprising:
the at least one load circuit;
the at least one clock buffer;
at least a portion of the oscillator circuit; and
multiple output nodes configured to be connected to the multiple clients, respectively.

14. The apparatus of claim 13 , further comprising:
a printed circuit board,
wherein the oscillator circuit comprises a resonator that is implemented on the printed circuit board and coupled to the integrated circuit.

15. An apparatus comprising:
supply means for providing a supply voltage;
oscillation means for generating a clock signal using the supply voltage; and
stabilization means for drawing current from the supply means during a portion of a period of the clock signal to adjusting adjust a magnitude of the supply voltage provided by the supply means by a particular amount, the stabilization means coupled to the oscillation means, the supply means, and a ground.

16. The apparatus of claim 15 , further comprising:
buffer means for selectively isolating the oscillation means from at least one client according to a disabled state or passing the clock signal to the at least one client according to an enabled state,
wherein the stabilization means is configured to adjust the magnitude of the supply voltage based on the buffer means being in the enabled state.

17. The apparatus of claim 15 , wherein the stabilization means comprises:
means for drawing current from the supply means during a portion of a period of the clock signal; and
capacitive means for controlling an amount of the current that is drawn from the supply means.

18. A method comprising:
generating a clock signal using a supply voltage;
passing the clock signal to different sets of clients, the different sets of clients associated with different loading conditions;
adjusting an average of the supply voltage by different amounts based on the different loading conditions; and
enabling at least one load circuit to draw power from the supply voltage to adjust the average of the supply voltage.

19. The method of claim 18 , wherein the adjusting the average of the supply voltage is effective to substantially stabilize a frequency of the clock signal during the different loading conditions.

20. The method of claim 18 , wherein the adjusting the average of the supply voltage comprises adjusting an amount of current the at least one load circuit draws from the supply voltage and routes to a ground.

21. An apparatus comprising:
multiple clients, each client of the multiple clients configured to:
selectively be in an enabled state or a disabled state; and
accept a clock signal in accordance with the enabled state; and

a clock generator coupled to the multiple clients and configured to generate the clock signal having a frequency that remains substantially stable responsive to providing the clock signal to a first set of the multiple clients that are in the enabled state during a first time interval and a second set of the multiple clients that are in the enabled state during a second time interval.

Assignees

• Qualcomm Inc

Inventors

• Iguchi Shunta
• Chi Xu
• Farias Michael Naone

Classifications

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title