Thin film transistor comprising oxide semiconductor layer and silicon semiconductor layer and display apparatus comprising the same

Patent metadata

Field	Value
Publication number	US-11495692-B2
Application number	US-202017121248-A
Country	US
Kind code	B2
Filing date	Dec 14, 2020
Priority date	Dec 26, 2019
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

Disclosed are a thin film transistor, a display apparatus comprising the thin film transistor, and a method for manufacturing the thin film transistor. The thin film transistor comprises an active layer, and a gate electrode spaced apart from the active layer and configured to have at least a portion overlapped with the active layer, wherein the active layer includes a silicon semiconductor layer, and an oxide semiconductor layer which contacts the silicon semiconductor layer, wherein at least a portion of the silicon semiconductor layer and at least a portion of the oxide semiconductor layer are overlapped with the gate electrode.

First claim

What is claimed is:

1. A thin film transistor comprising:
an active layer; and
a gate electrode spaced apart from the active layer and configured to have at least a portion overlapped with the active layer,
wherein the active layer includes:
a silicon semiconductor layer; and
an oxide semiconductor layer which contacts the silicon semiconductor layer,
wherein at least a portion of the silicon semiconductor layer and at least a portion of the oxide semiconductor layer are overlapped with the gate electrode, and
wherein the silicon semiconductor layer is provided while being not overlapped with the oxide semiconductor layer in a corresponding area of 50% or more of an overlap area between the active layer and the gate electrode.

2. The thin film transistor according to claim 1 , wherein the silicon semiconductor layer and the oxide semiconductor layer are disposed on a same layer.

3. The thin film transistor according to claim 1 , wherein an entire area of a contact portion where the silicon semiconductor layer and the oxide semiconductor layer contact each other is overlapped with the gate electrode.

4. The thin film transistor according to claim 1 , wherein at least a portion of the oxide semiconductor layer is overlapped with the silicon semiconductor layer in a thickness direction.

5. The thin film transistor according to claim 1 , wherein the silicon semiconductor and the oxide semiconductor layer are not overlapped with each other in a thickness direction.

6. The thin film transistor according to claim 5 , wherein a lateral surface of the oxide semiconductor layer contacts a lateral surface of the silicon semiconductor layer.

7. The thin film transistor according to claim 1 , wherein the silicon semiconductor layer is provided to be 50% or more of the overlap area between the active layer and the gate electrode.

8. The thin film transistor according to claim 1 , further comprising:
a source electrode and a drain electrode which are spaced apart from each other and are respectively connected with the active layer,
wherein any one of the source electrode and the drain electrode is connected with the silicon semiconductor layer, and
the other of the source electrode and the drain electrode is connected with the oxide semiconductor layer.

9. The thin film transistor according to claim 1 , wherein the active layer includes:
a channel portion which is overlapped with the gate electrode;
a source region which is connected with the channel portion and is not overlapped with the gate electrode; and
a drain region which is spaced apart from the source region and connected with the channel region, and is not overlapped with the gate electrode,
wherein, a distance between the source region and the drain region in the channel portion is referred to as a channel length, and wherein a length of a portion of the silicon semiconductor layer being not overlapped with the oxide semiconductor layer is 50% to 90% of the channel length.

10. The thin film transistor according to claim 9 , wherein the oxide semiconductor layer which is not overlapped with the silicon semiconductor layer is provided in at least some regions of the channel portion along a line configured to connect the source region and the drain region with each other.

11. The thin film transistor according to claim 9 , wherein any one of the source region and the drain region is provided in the silicon semiconductor layer, and the other of the source region and the drain region is provided in the oxide semiconductor layer.

12. The thin film transistor according to claim 1 , wherein the oxide semiconductor layer includes:
a first oxide semiconductor layer; and
a second oxide semiconductor layer on the first oxide semiconductor layer.

13. The thin film transistor according to claim 1 , wherein the oxide semiconductor layer is disposed at each of one side and the other side of the silicon semiconductor layer.

14. A display apparatus comprising the thin film transistor of claim 1 .

15. The display apparatus according to claim 14 , wherein the thin film transistor is a driving transistor.

16. A method for manufacturing a thin film transistor comprising:
providing an active layer on a substrate;
providing a gate electrode having at least a portion overlapped with the active layer; and
providing selective conductivity for the active layer by using the gate electrode as a mask,
wherein providing the active layer comprises:
providing a silicon semiconductor layer on the substrate; and
providing an oxide semiconductor layer which contacts the silicon semiconductor layer on the substrate,
wherein the gate electrode is overlapped with at least a portion of the silicon semiconductor layer and at least a portion of the oxide semiconductor layer.

17. The method according to claim 16 , wherein the selective conductivity providing process for the active layer includes doping a portion of the active layer, which is not overlapped with the gate electrode, with ions.

Assignees

• Lg Display Co Ltd

Inventors

• Jang Jaeman
• Yun Pilsang
• Noh Jiyong
• Cho Intak

Classifications

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• G02F1/136277

  formed on a semiconductor substrate, e.g. of silicon · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L29/78693 Primary

  Electricity · mapped topic

• H01L29/78618

  Electricity · mapped topic