Image processing circuit and method for compensating for IR drop on display panel

US11495177B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11495177-B2
Application numberUS-202117368838-A
CountryUS
Kind codeB2
Filing dateJul 7, 2021
Priority dateJul 12, 2020
Publication dateNov 8, 2022
Grant dateNov 8, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

The present invention provides an image processing circuit for compensating image data for a display panel used for displaying first and second image patterns respectively having first and second current loadings. The image processing circuit is used for: receiving a first original image data of the first image pattern and a second original image data of the second image pattern having the same brightness value for a pixel at the same location; converting the first original image data into a first final image data to compensate for an IR drop according to the first current loading; and converting the second original image data into a second final image data to compensate for the IR drop according to the second current loading. The first final image data and the second final image data have substantially the same brightness value for the pixel at the same location.

First claim

Opening claim text (preview).

What is claimed is: 1. An image processing circuit for compensating image data for a display panel, the display panel used for displaying a first image pattern having a first current loading and a second image pattern having a second current loading different from the first current loading, and the image processing circuit being used for: receiving a first original image data of the first image pattern and a second original image data of the second image pattern, wherein the first original image data and the second original image data have the same brightness value for a pixel at the same location of the first image pattern and the second image pattern; converting the first original image data into a first final image data to compensate for a voltage drop of the first image pattern according to the first current loading, to display the first image pattern based on the first final image data; converting the second original image data into a second final image data to compensate for a voltage drop of the second image pattern according to the second current loading, to display the second image pattern based on the second final image data; comparing the first current loading with a default current loading, to determine a current ratio corresponding to the first current loading; and determining a correction value for a compensation value of the voltage drop of the first image pattern according to the current ratio; wherein the first final image data and the second final image data have substantially the same brightness value for the pixel at the same location of the first image pattern and the second image pattern. 2. The image processing circuit of claim 1 , wherein the first current loading is a total current consumption on the display panel generated by the first image pattern, and the second current loading is a total current consumption on the display panel generated by the second image pattern. 3. The image processing circuit of claim 1 , wherein the default current loading is a current loading generated by an all-white image pattern. 4. The image processing circuit of claim 1 , wherein the correction value is obtained from a lookup table, which records a plurality of correction values corresponding to a plurality of current ratios, respectively. 5. The image processing circuit of claim 1 , wherein the correction value for the compensation value of the voltage drop of the first image pattern generates a deduction on the compensation value. 6. The image processing circuit of claim 1 , wherein the first current loading corresponds to a first correction value for a first compensation value of the voltage drop of the first image pattern, and the second current loading corresponds to a second correction value for a second compensation value of the voltage drop of the second image pattern, wherein the first correction value is greater than the second correction value when the first current loading is less than the second current loading. 7. An image processing circuit for compensating image data for a display panel, the display panel used for displaying an image pattern having a current loading, and the image processing circuit being used for: receiving an original image data of the image pattern to be displayed on the display panel; generating a compensation value for the original image data according to a voltage drop generated by the image pattern; generating a correction value according to the current loading; compensating the original image data with the correction value and the compensation value to generate a final image data; and driving the display panel based on the final image data, to control the display panel to display the image pattern; wherein the step of generating the correction value according to the current loading comprises: comparing the current loading with a default current loading, to determine a current ratio corresponding to the current loading; and determining the correction value for the compensation value according to the current ratio. 8. The image processing circuit of claim 7 , wherein the current loading is a total current consumption on the display panel generated by the image pattern. 9. The image processing circuit of claim 7 , wherein the default current loading is a current loading generated by an all-white image pattern. 10. The image processing circuit of claim 7 , wherein the correction value is obtained from a lookup table, which records a plurality of correction values corresponding to a plurality of current ratios, respectively. 11. The image processing circuit of claim 10 , wherein among the plurality of correction values, a first correction value corresponds to a first current loading and a second correction value corresponds to a second current loading, wherein the first correction value is greater than the second correction value when the first current loading is less than the second current loading. 12. The image processing circuit of claim 7 , wherein the correction value for the compensation value generates a deduction on the compensation value. 13. A method of compensating image data for a display panel displaying an image pattern having a current loading, the method comprising: receiving an original image data of the image pattern to be displayed on the display panel; generating a compensation value for the original image data according to a voltage drop generated by the image pattern; generating a correction value according to the current loading; compensating the original image data with the correction value and the compensation value to generate a final image data; and driving the display panel based on the final image data, to control the display panel to display the image pattern; wherein the step of generating the correction value according to the current loading comprises: comparing the current loading with a default current loading, to determine a current ratio corresponding to the current loading; and determining the correction value for the compensation value according to the current ratio. 14. The method of claim 13 , wherein the current loading is a total current consumption on the display panel generated by the image pattern. 15. The method of claim 13 , wherein the default current loading is a current loading generated by an all-white image pattern. 16. The method of claim 13 , wherein the correction value is obtained from a lookup table, which records a plurality of correction values corresponding to a plurality of current ratios, respectively. 17. The method of claim 16 , wherein among the plurality of correction values, a first correction value corresponds to a first current loading and a second correction value corresponds to a second current loading, wherein the first correction value is greater than the second correction value when the first current loading is less than the second current loading. 18. The method of claim 13 , wherein the correction value for the compensation value generates a deduction on the compensation value.

Assignees

Inventors

Classifications

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • G09G3/3208Primary

    organic, e.g. using organic light-emitting diodes [OLED] · CPC title

  • Improving the quality of display appearance · CPC title

  • Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11495177B2 cover?
The present invention provides an image processing circuit for compensating image data for a display panel used for displaying first and second image patterns respectively having first and second current loadings. The image processing circuit is used for: receiving a first original image data of the first image pattern and a second original image data of the second image pattern having the same…
Who is the assignee on this patent?
Novatek Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).