System and method for accelerated ray tracing with asynchronous operation and ray transformation

Patent metadata

Field	Value
Publication number	US-11494969-B2
Application number	US-202016998212-A
Country	US
Kind code	B2
Filing date	Aug 20, 2020
Priority date	Aug 20, 2020
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives asynchronously with shader operation. The RTU implements traversal logic to traverse the acceleration structure including transformation of rays as needed to account for variations in coordinate space between levels, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

First claim

What is claimed is:

1. A method for graphics processing, comprising:
executing, on a graphics processing unit (GPU), a shader program that performs ray tracing of a 3D environment represented by an acceleration structure;
asynchronous to the shader program, using a hardware-implemented ray tracing unit (RTU) within the GPU that traverses the acceleration structure at the request of the shader program; and
using, at the shader program, results of the acceleration structure traversal;
wherein the shader program is configured to send root node and information related to rays to the RTU to initiate processing in which the RTU is configured to begin traversing the acceleration structure asynchronously to shader program operation, with the shader program reading at least one status of the RTU periodically and the RTU reporting the at least one status as it continues its traversal, the shader program passing hit identifications to the RTU to enable the RTU to shorten rays, the at least one status from the RTU to the shader program indicating the RTU has not found any intersections yet, at least a second status from the RTU indicating that the RTU has found an intersection with a first primitive, the shader program performing hit testing and responsive to finding that the first primitive was hit by a ray, informs the RTU of the hit so that the RTU can shorten the ray.

2. The method of claim 1 , wherein using the results comprises shading pixels in computer-generated graphics.

3. The method of claim 1 , wherein the results of the acceleration structure traversal by the RTU include the detection of intersection between a first ray and bounding volumes contained within the acceleration structure, and/or intersection between a second ray and primitives contained within the acceleration structure.

4. The method of claim 3 , wherein the results of the acceleration structure traversal by the RTU include detection of the earliest intersection between a first ray and primitives contained within the acceleration structure.

5. The method of claim 1 , where the RTU processing includes maintenance of a stack used in the acceleration structure traversal.

6. The method of claim 1 , wherein the results of the acceleration structure traversal by the RTU include a sorting by the RTU of the intersections detected by the RTU, by distance of the intersections from ray origin, such that:
the RTU detects a first intersection between a first ray and a primitive as it traverses the acceleration structure; and
the RTU detects a second intersection between the first ray and a primitive as it traverses the acceleration structure; and
when communicating results from the RTU to the shader program, the second intersection result is communicated before the first intersection result, which also is communicated to the shader program.

7. A method for graphics processing, comprising:
executing, on a graphics processing unit (GPU), a shader program that performs ray tracing of a 3D environment represented by an acceleration structure;
using a hardware-implemented ray tracing unit (RTU) within the GPU that traverses the acceleration structure at the request of the shader program; and
using, at the shader program, results of the acceleration structure traversal, wherein the acceleration structure is a hierarchy with a plurality of levels, wherein the RTU identifies intersections of rays with elements in the acceleration structure, indicates intersections to the shader program, and the shader program performs hit testing, determining whether a ray passed through a transparent portion of an element or hit a non-transparent portion of the element, the RTU sorting intersections by distance, the shader program receiving a status that the RTU has found an intersection with a first primitive, the shader program performing hit testing on the first primitive and responsive to determining the first primitive was hit by the ray, informs the RTU so that the RTU can shorten the ray, the RTU determining intersections with second and third primitives, the third primitive being closer to a ray origin than the second primitive, the shader program accessing RTU information to perform hit testing on the third primitive and not on the second primitive.

8. The method of claim 7 , wherein using the results comprises shading pixels in computer-generated graphics.

9. The method of claim 7 , wherein the results of the acceleration structure traversal by the RTU include detection of a transition from a higher level to a lower level within the plurality of levels of the acceleration structure.

10. The method of claim 7 , wherein the results of the acceleration structure traversal by the RTU include detection of a transition from a lower level to a higher level within the plurality of levels of the acceleration structure.

11. A graphic processing unit (GPU) comprising:
at least one processor core adapted to execute a software-implemented shader; and
at least one hardware-implemented ray tracing unit (RTU) separate from the processor core and adapted to traverse an acceleration structure asynchronously with respect to shader operation to identify intersections of rays with objects represented in the acceleration structure to generate results and return the results to the shader for identification by the shader of hits associated with the intersections wherein the shader is configured to send root node and ray information to the RTU to initiate processing in which the RTU is configured to begin traversing the acceleration structure asynchronously to shader operation, with the shader being configured for reading at least one status of the RTU periodically, the shader being configured for passing hit identifications to the RTU to enable the RTU to shorten rays, at least a first status from the RTU to the shader indicating the RTU has not found any intersections yet, at least a second status from the RTU indicating that the RTU has found an intersection with a first primitive, the shader being configured for performing hit testing and responsive to finding that the first primitive was hit by a ray, the shader being configured for informing the RTU of the hit so that the RTU can shorten the ray.

12. The GPU of claim 11 , wherein the RTU comprises hardware circuitry to identify the intersections and the shader is adapted to identify the hits using software.

13. The GPU of claim 11 , wherein the shader is configured with instructions executable by the processor core to shade pixels in 3D computer graphics.

14. The GPU of claim 11 , wherein the RTU comprises hardware circuitry to implement traversal logic to traverse the acceleration structure.

15. The GPU of claim 11 , wherein the RTU comprises hardware circuitry to implement stack management of a stack used in traversal of the acceleration structure.

16. A graphic processing unit (GPU) comprising:
at least one processor core adapted to execute a software-implemented shader; and
at least one hardware-implemented ray tracing unit (RTU) separate from the processor core and adapted to traverse an acceleration structure to identify intersections of rays with objects represented in the acceleration structure to generate results and return the results to the shader, the shader being configured for receiving a first status that the RTU has found an intersection with a first primitive, the shader configured for performing hit testing on the first primitive and responsive to determining the first primitive was hit by the ray, the shader being configured for informing the RTU so that the RTU can shorten the ray, the RTU configured for dete

Assignees

• Sony Interactive Entertainment LLC

Inventors

• Cerny Mark Evan

Classifications

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06T15/205

  Image-based rendering · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T15/50

  Lighting effects · CPC title