Method, device and computer program product for thread management

US11494185B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11494185-B2
Application numberUS-202117207806-A
CountryUS
Kind codeB2
Filing dateMar 22, 2021
Priority dateJan 6, 2021
Publication dateNov 8, 2022
Grant dateNov 8, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Techniques for managing threads involve acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads, and determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information. The techniques further involve providing an indication that a deadlock exists in the plurality of threads if it is determined that a first group of runtime addresses of the first group of lock objects overlaps with a second group of runtime addresses of the second group of lock objects. Accordingly, potential deadlocks in a plurality of threads can be analyzed, thereby avoiding the inability of the threads to proceed normally due to the deadlocks.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for managing threads, comprising: acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads; determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information; and providing an indication that a deadlock exists in the plurality of threads if it is determined that a first group of runtime addresses of the first group of lock objects overlaps with a second group of runtime addresses of the second group of lock objects. 2. The method according to claim 1 , wherein providing the indication comprises: sorting the first group of lock objects and the second group of lock objects according to the first group of runtime addresses and the second group of runtime addresses; and providing the indication if it is determined that a first lock object in the first group of lock objects is ranked lower than a second lock object in the second group of lock objects. 3. The method according to claim 1 , wherein the first group of lock objects corresponds to a first lock in a static code, and the second group of lock objects corresponds to a second lock in the static code and different from the first lock. 4. The method according to claim 3 , wherein a first static address of the first lock in a code segment is located before a second static address of the second lock in the code segment. 5. The method according to claim 3 , wherein the indication comprises a name of the first lock and a name of the second lock. 6. The method according to claim 3 , wherein the first call information comprises a first jump address corresponding to the first lock, and the second call information comprises a second jump address corresponding to the second lock. 7. The method according to claim 6 , further comprising: disassembling constructor functions of the first lock and the second lock to determine the first jump address and the second jump address. 8. An electronic device, comprising: at least one processor; and at least one memory storing computer program instructions, the at least one memory and the computer program instructions being configured to cause, together with the at least one processor, the electronic device to perform actions comprising: acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads; determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information; and providing an indication that a deadlock exists in the plurality of threads if it is determined that a first group of runtime addresses of the first group of lock objects overlaps with a second group of runtime addresses of the second group of lock objects. 9. The electronic device according to claim 8 , wherein providing the indication comprises: sorting the first group of lock objects and the second group of lock objects according to the first group of runtime addresses and the second group of runtime addresses; and providing the indication if it is determined that a first lock object in the first group of lock objects is ranked lower than a second lock object in the second group of lock objects. 10. The electronic device according to claim 8 , wherein the first group of lock objects corresponds to a first lock in a static code, and the second group of lock objects corresponds to a second lock in the static code and different from the first lock. 11. The electronic device according to claim 10 , wherein a first static address of the first lock in a code segment is located before a second static address of the second lock in the code segment. 12. The electronic device according to claim 10 , wherein the indication comprises a name of the first lock and a name of the second lock. 13. The electronic device according to claim 10 , wherein the first call information comprises a first jump address corresponding to the first lock, and the second call information comprises a second jump address corresponding to the second lock. 14. The electronic device according to claim 13 , wherein the actions further comprise: disassembling constructor functions of the first lock and the second lock to determine the first jump address and the second jump address. 15. A computer program product having a non-transitory computer readable medium which stores a set of instructions to manage threads; the set of instructions, when carried out by computerized circuitry, causing the computerized circuitry to perform a method of: acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads; determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information; and providing an indication that a deadlock exists in the plurality of threads if it is determined that a first group of runtime addresses of the first group of lock objects overlaps with a second group of runtime addresses of the second group of lock objects.

Assignees

Inventors

Classifications

  • Synchronisation or serialisation instructions · CPC title

  • Formation of subprogram jump address · CPC title

  • Manager · CPC title

  • G06F9/524Primary

    Deadlock detection or avoidance · CPC title

  • G06F9/3009Primary

    Thread control instructions · CPC title

Patent family

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Frequently asked questions

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What does patent US11494185B2 cover?
Techniques for managing threads involve acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads, and determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information.…
Who is the assignee on this patent?
Emc Ip Holding Co Llc
What technology area does this patent fall under?
Primary CPC classification G06F9/524. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).