Display panel test circuit

US11493552B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11493552-B2
Application numberUS-202117191581-A
CountryUS
Kind codeB2
Filing dateMar 3, 2021
Priority dateMar 10, 2020
Publication dateNov 8, 2022
Grant dateNov 8, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel test circuit includes a first transistor connected to a first data line and receiving a red lighting test signal, a second transistor connected to the first data line and receiving a blue lighting test signal, a third transistor connected to a second data line and receiving a first green lighting test signal, a fourth transistor connected to a third data line and receiving the red lighting test signal, a fifth transistor connected to the third data line and receiving the blue lighting test signal, a sixth transistor connected to a fourth data line and receiving a second green lighting test signal, a seventh transistor connected to the second data line and receiving a crack test signal, and an eighth transistor connected to the fourth data line and receiving the crack test signal. The display panel test circuit performs one or more tests on a display panel.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel test circuit comprising: a first transistor including a first terminal connected to a first data line to which a first red sub-pixel and a first blue sub-pixel are connected, a gate terminal that receives a red lighting test signal, and a second terminal connected to a red lighting voltage line that supplies a red lighting voltage; a second transistor including a first terminal connected to the first data line, a gate terminal that receives a blue lighting test signal, and a second terminal connected to a blue lighting voltage line that supplies a blue lighting voltage; a third transistor including a first terminal connected to a second data line to which first green sub-pixels are connected, a gate terminal that receives a first green lighting test signal, and a second terminal connected to a green lighting voltage line that supplies a green lighting voltage; a fourth transistor including a first terminal connected to a third data line to which a second red sub-pixel and a second blue sub-pixel are connected, a gate terminal that receives the red lighting test signal, and a second terminal connected to the blue lighting voltage line; a fifth transistor including a first terminal connected to the third data line, a gate terminal that receives the blue lighting test signal, and a second terminal connected to the red lighting voltage line; a sixth transistor including a first terminal connected to a fourth data line to which second green sub-pixels are connected, a gate terminal that receives a second green lighting test signal, and a second terminal connected to the green lighting voltage line; a seventh transistor including a first terminal connected to the second data line, a gate terminal that receives a crack test signal, and a second terminal connected to a crack detection line that passes through a non-display region of a display panel; and an eighth transistor including a first terminal connected to the fourth data line, a gate terminal that receives the crack test signal, and a second terminal connected to the crack detection line. 2. The display panel test circuit of claim 1 , wherein the display panel test circuit performs a lighting test on the display panel based on the red lighting test signal, the blue lighting test signal, the first green lighting test signal, and the second green lighting test signal having a turn-on voltage level, the red lighting voltage, the blue lighting voltage, and the green lighting voltage having a lighting voltage level, and the crack test signal having a turn-off voltage level. 3. The display panel test circuit of claim 1 , wherein the display panel test circuit performs a first open-short test on the display panel based on the red lighting test signal and the second green lighting test signal having a turn-on voltage level, the first green lighting test signal and the blue lighting test signal having a turn-off voltage level, the red lighting voltage having a non-lighting voltage level, the blue lighting voltage and the green lighting voltage having a lighting voltage level, and the crack test signal having the turn-on voltage level. 4. The display panel test circuit of claim 3 , wherein the display panel test circuit performs a second open-short test on the display panel based on the red lighting test signal and the first green lighting test signal having the turn-on voltage level, the second green lighting test signal and the blue lighting test signal having the turn-off voltage level, the blue lighting voltage having the non-lighting voltage level, the red lighting voltage and the green lighting voltage having the lighting voltage level, and the crack test signal having the turn-on voltage level. 5. The display panel test circuit of claim 1 , wherein the display panel test circuit performs a crack test on the display panel, one of the red lighting test signal and the blue lighting test signal has a turn-on voltage level, another of the red lighting test signal and the blue lighting test signal has a turn-off voltage level, the first green lighting test signal and the second green lighting test signal have the turn-off voltage level, the red lighting voltage, the blue lighting voltage, and the green lighting voltage have a non-lighting voltage level, and the crack test signal has the turn-on voltage level. 6. The display panel test circuit of claim 1 , further comprising: a ninth transistor including a first terminal connected to the first data line, a gate terminal that receives a first pre-lighting test signal, and a second terminal connected to a pre-lighting test pad; a tenth transistor including a first terminal connected to the second data line, a gate terminal that receives a second pre-lighting test signal, and a second terminal connected to the pre-lighting test pad; an eleventh transistor including a first terminal connected to the third data line, a gate terminal that receives a third pre-lighting test signal, and a second terminal connected to the pre-lighting test pad; and a twelfth transistor including a first terminal connected to the fourth data line, a gate terminal that receives a fourth pre-lighting test signal, and a second terminal connected to the pre-lighting test pad. 7. The display panel test circuit of claim 6 , wherein the display panel test circuit performs a pre-lighting test on the display panel based on the red lighting test signal, the blue lighting test signal, the first green lighting test signal, and the second green lighting test signal having a turn-off voltage level, the crack test signal having the turn-off voltage level, the first pre-lighting test signal, the second pre-lighting test signal, the third pre-lighting test signal, and the fourth pre-lighting test signal having a turn-on voltage level, and a pre-lighting voltage having a lighting voltage level and applied via the pre-lighting test pad. 8. The display panel test circuit of claim 6 , wherein the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are arranged between the green lighting voltage line and the blue lighting voltage line, between the green lighting voltage line and the red lighting voltage line, or between the blue lighting voltage line and the red lighting voltage line. 9. A display panel test circuit comprising: a first transistor including a first terminal connected to a first data line to which a first red sub-pixel and a first blue sub-pixel are connected, a gate terminal that receives a red lighting test signal, and a second terminal connected to a red lighting voltage line that supplies a red lighting voltage; a second transistor including a first terminal connected to the first data line, a gate terminal that receives a blue lighting test signal, and a second terminal connected to a blue lighting voltage line that supplies a blue lighting voltage; a third transistor including a first terminal connected to a second data line to which first green sub-pixels are connected, a gate terminal that receives a first green lighting test signal, and a second terminal connected to both a pre-lighting test pad and a green lighting voltage line that supplies a green lighting voltage; a fourth transistor including a first terminal connected to a third data line to which a second red sub-pixel and a second blue sub-pixel are connected, a gate terminal that receives the red lighting test signal, and a second terminal connected to the blue lighting voltage line; a fifth transistor including a first terminal connected to the third data line, a gate terminal that receives the blue lighting test signal, and a second terminal connected to the red lighting voltage line; a sixth transistor including a first terminal

Assignees

Inventors

Classifications

  • Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

  • Input or output aspects · CPC title

  • Display of colours (specific for liquid crystal displays G09G3/3607) · CPC title

  • G09G3/006Primary

    Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

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What does patent US11493552B2 cover?
A display panel test circuit includes a first transistor connected to a first data line and receiving a red lighting test signal, a second transistor connected to the first data line and receiving a blue lighting test signal, a third transistor connected to a second data line and receiving a first green lighting test signal, a fourth transistor connected to a third data line and receiving the r…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G01R31/31712. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).