Flip-chip package substrate

Patent metadata

Field	Value
Publication number	US-11488911-B2
Application number	US-201816049893-A
Country	US
Kind code	B2
Filing date	Jul 31, 2018
Priority date	May 7, 2018
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A flip-chip package substrate is provided. A strengthening structure is provided on one side of a circuit structure to increase the rigidity of the flip-chip package substrate. When the flip-chip package substrate is used in large-scale packaging, the flip-chip package substrate can have good rigidity, so that the electronic package can be prevented from warping.

First claim

What is claimed is:

1. A flip-chip package substrate, comprising:
a circuit structure including a first side and a second side opposite to the first side, wherein either one of the first side or the second side of the circuit structure is used as a chip side for electronic components to be placed thereon, wherein the circuit structure further includes a core layer, and at least one dielectric layer and a circuit layer are formed on the core layer, and wherein the core layer includes a plurality of conductive portions electrically connected with the circuit layer, and the circuit layer has the same number of layers on upper and lower sides of the core layer;
a strengthening structure having a top surface and a bottom surface and disposed on the second side of the circuit structure, wherein the top surface of the strengthening structure is bonded with the second side of the circuit structure and the bottom surface of the strengthening structure is free from being bonded with other circuit structures, wherein the strengthening structure is free from being electrically connected with the circuit structure, the strengthening structure includes a rigid layer made of a conductive material or an insulating material and an insulating portion covering the rigid layer, and the rigid layer is bonded onto the circuit structure by the insulating portion; and
conductive elements having a top end and a bottom end and disposed on and electrically connected with the circuit structure, wherein the conductive elements are of a pillar-shaped structure and are positioned in the strengthening structure, wherein the top end of the conductive elements is connected with the circuit structure, and wherein the bottom end of the conductive elements is exposed from the strengthening structure and free from being bonded with other circuit structures.

2. The flip-chip package substrate of claim 1 , wherein the conductive portions each include a single pillar or a plurality of stacked pillars in contact with one another.

3. The flip-chip package substrate of claim 1 , wherein the conductive portions are conductive through holes.

4. The flip-chip package substrate of claim 1 , wherein the insulating portion includes a bonding layer bonded to the circuit structure and a protective layer covering the rigid layer.

5. An electronic package, comprising:
the flip-chip package substrate of claim 1 ; and
an electronic component disposed on at least one of the first side and the second side of the circuit structure,
wherein the conductive portions each are a conductive through hole, a single pillar, or a plurality of stacked pillars in contact with one another.

6. The electronic package of claim 5 , further comprising an encapsulating layer disposed on the circuit structure, wherein the encapsulating layer covers and is bonded to the electronic component.

7. The electronic package of claim 5 , wherein the insulating portion includes a bonding layer bonded to the circuit structure and a protective layer covering the rigid layer.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hu Chu-Chin
• Hsu Shih-Ping

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117 Primary

  the substrate having spherical bumps for external connection · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title