Encoders, decoders, and semiconductor memory devices including the same

Patent metadata

Field	Value
Publication number	US-11488646-B2
Application number	US-202016909177-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Nov 13, 2019
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

First claim

What is claimed is:

1. An encoder comprising:
an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data; and
an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state that are included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state that are included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal,
wherein n is at least 2 and m is at least 3.

2. The encoder of claim 1 , wherein, responsive to the number of first bits or the number of second bits indicating the first state being 0, the output driver is further configured to not transmit the voltage and/or the current or to be connected to a ground voltage.

3. The encoder of claim 1 , wherein the encoding unit is further configured to convert n-bit first read data of the 2n-bit read data into the m-bit first read data and to convert n-bit second read data of the 2n-bit read data into the m-bit second read data.

4. The encoder of claim 3 , wherein the output driver comprises:
a clock signal generator configured to sequentially generate m clock signals using the clock signal during each of the activation period of the clock signal and the deactivation period of the clock signal;
a pulse signal generator configured to sequentially generate k first pulse signals based on the m clock signals and the m-bit first read data during the activation period of the clock signal and to sequentially generate j second pulse signals based on the m clock signals and the m-bit second read data during the deactivation period of the clock signal; and
a driver configured to drive the voltage and/or the current k times in response to the k first pulse signals and to drive the voltage and/or the current j times in response to the j second pulse signals,
wherein k is the number of first bits, j is the number of second bits, and each of k and j is at least 0 and at most m.

5. The encoder of claim 3 , wherein the output driver comprises:
a pulse signal generator configured to generate k first pulse signals based on the m-bit first read data during the activation period of the clock signal and to generate j second pulse signals based on the m-bit second read data during the deactivation period of the clock signal; and
a driver configured to drive the current corresponding to the number of first bits in response to the k first pulse signals and to drive the current corresponding to the number of second bits in response to the j second pulse signals,
wherein k is the number of first bits, j is the number of the second bits, and each of k and j is at least 0 and at most m.

6. A semiconductor memory device comprising:
a row decoder configured to generate a plurality of word line selection signals in response to a row address;
a column decoder configured to generate a plurality of column selection signals in response to a column address;
a memory cell array comprising a plurality of memory cells, and configured to generate multi-bit read data from selected memory cells among the plurality of memory cells in response to the plurality of word line selection signals and the plurality of column selection signals and/or to store multi-bit write data from the selected memory cells;
a read path unit configured to receive the multi-bit read data and to generate 2n-bit read data during a read operation; and
an encoder configured to receive the 2n-bit read data to generate 2m-bit read data during the read operation, to transmit current and/or voltage a first number of times corresponding to a number of first bits indicating a first state that are included in m-bit first read data of the 2m-bit read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the current and/or the voltage a second number of times corresponding to a number of second bits indicating the first state that are included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal,
wherein n is at least 2 and m is at least 3.

7. The semiconductor memory device of claim 6 , wherein the encoder comprises:
an encoding unit configured to receive the 2n-bit read data and to generate the 2m-bit read data; and
an output driver configured to input the m-bit first read data, to transmit the voltage and/or the current the first number of times corresponding to the number of first bits or to transmit the current corresponding to the number of first bits during the activation period of the clock signal, and to transmit the voltage and/or the current the second number of times corresponding to the number of second bits or to transmit the current corresponding to the number of second bits during the deactivation period of the clock signal.

8. The semiconductor memory device of claim 7 , wherein, responsive to the number of first bits or the number of second bits being 0, the output driver is further configured to not transmit the voltage and/or the current or is connected to ground voltage.

9. The semiconductor memory device of claim 7 , wherein the encoding unit comprises a multi-bit converter configured to convert n-bit first read data of the 2n-bit read data into the m-bit first read data and to convert n-bit second read data of the 2n-bit read data into the m-bit second read data.

10. The semiconductor memory device of claim 9 , wherein the output driver comprises:
a clock signal generator configured to sequentially generate m clock signals using the clock signal during each of the activation period of the clock signal and the deactivation period of the clock signal;
a pulse signal generator configured to sequentially generate k first pulse signals based on the m clock signals and the m-bit first read data during the activation period of the clock signal and to sequentially generate j second pulse signals based on the m clock signals and the m-bit second read data during the deactivation period of the clock signal; and
a driver configured to drive the voltage and/or the current k times in response to the k first pulse signals and to drive the voltage and/or the current j times in response to the j second pulse signals,
wherein k is the number of first bits, j is the number of second bits, and each of k and j is at least 0 and at most m.

11. The semiconductor memory device of claim 9 , wherein the output driver comprises:
a pulse signal generator configured to generate k first pulse signals based on the m-bit first read data during the activation period of the clock signal and to generate j second pulse signals based on the m-bit second read data during the deactivation period of the clock signal; and
a driver configured to drive the current corresponding to the number of first bits in response to the k first pulse signals and to drive the current corresponding to the number of second bits in response to the j second pulse signals,
wherein k is the number of first bits, j is the number of second bits, and each of k and j is at least 0 and at most m.

12. The semiconductor memory device of claim 6 , wherein the number of first bits indicating the first state that are included in the m-bit fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Byongmo

Classifications

• G11C7/1093

  Input synchronization · CPC title

• G11C8/10 Primary

  Decoders · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title