Pattern matching using anchors during integrated circuit verification

Patent metadata

Field	Value
Publication number	US-11487930-B2
Application number	US-202017085727-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	Oct 30, 2019
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

Pattern matching using anchors during integrated circuit (IC) verification is disclosed. According to one embodiment, a method includes obtaining match time estimates associated with pattern anchors of different anchor types for an IC pattern, generating revised match time estimates based on a target IC layout, and then selecting the pattern anchor associated with the shortest revised match time estimate. Then, target anchors of the same anchor type as the selected pattern anchor are generated for the target IC layout, and the target IC layout is searched for the IC pattern using the selected pattern anchor and the target anchors.

First claim

What is claimed is:

1. A method, comprising:
receiving, by one or more processors, a first match time estimate associated with a first pattern anchor of a first anchor type of a plurality of anchor types within an integrated circuit (IC) pattern;
receiving, by the one or more processors, a second match time estimate associated with a second pattern anchor of a second anchor type of the plurality of anchor types within the IC pattern;
determining whether the first match time estimate is shorter than the second time estimate;
in response to determining that the first match time estimate is shorter than the second time estimate, generating, by the one or more processors, a plurality of target anchors of the first anchor type within a layer of a target IC layout; and
searching, by the one or more processors, the target IC layout for the IC pattern using the first pattern anchor and the plurality of target anchors.

2. The method of claim 1 , wherein the first anchor type is associated with a dimension parameter.

3. The method of claim 1 , further comprising:
generating a plurality of candidate anchors of the first anchor type for the IC pattern;
determining a plurality of distances between a center of the IC pattern and the plurality of candidate anchors; and
selecting the first pattern anchor from the plurality of candidate anchors based on a distance between the center of the IC pattern and the first pattern anchor.

4. The method of claim 1 , further comprising:
calculating the first match time estimate based on an anchor generation time for the first anchor type, a number of candidate anchors of the first anchor type in the IC pattern, and an average match time.

5. The method of claim 1 , further comprising:
generating an estimate of a number of target anchors of the first anchor type in the layer of the target IC layout;
calculating a ratio of the estimate to a number of candidate anchors of the first anchor type in the IC pattern;
revising the first match time estimate by scaling the first match time estimate based on the ratio; and
revising the second match time estimate.

6. The method of claim 5 , wherein the plurality of anchor types includes a vertex or a 90° concave vertex, and wherein generating the estimate comprises counting a number of polygons in the layer.

7. The method of claim 5 , wherein the plurality of anchor types includes a rectangle shape, an enclosing, a non-rectangular shape, or a line end shape, and wherein generating the estimate comprises counting a number of polygons in the layer of the first anchor type.

8. The method of claim 5 , wherein the plurality of anchor types includes a 45° vertex or a 45° concave vertex, and wherein generating the estimate comprises identifying non-orthogonal polygons in the layer and doubling the trapezoid number of the non-orthogonal polygons.

9. The method of claim 1 , further comprising:
detecting a process hotspot based on searching the layer of the target IC layout.

10. A system, comprising:
a memory; and
a processor operatively connected to the memory and configured to:
receive a first match time estimate associated with a first pattern anchor of a first anchor type of a plurality of anchor types within an integrated circuit (IC) pattern;
receive a second match time estimate associated with a second pattern anchor of a second anchor type of the plurality of anchor types within the IC pattern;
determine whether the first match time estimate is shorter than the second match time estimate;
in response to the first match time estimate being shorter than the second match time estimate, generate a plurality of target anchors of the first anchor type within a layer of a target IC layout; and
search the target IC layout for the IC pattern using the first pattern anchor and the plurality of target anchors.

11. The system of claim 10 , wherein the first anchor type is associated with a dimension parameter.

12. The system of claim 10 , wherein the processor is further configured to:
generate an estimate of a number of target anchors of the first anchor type in the layer of the target IC layout;
calculate a ratio of the estimate to a number of candidate anchors of the first anchor type in the IC pattern;
revise the first match time estimate by scaling the first match time estimate based on the ratio; and
revise the second match time estimate.

13. The system of claim 12 , wherein the plurality of anchor types includes a vertex or a 90° concave vertex, and wherein the estimate is generated by at least counting a number of polygons in the layer.

14. The system of claim 12 , wherein the plurality of anchor types includes a rectangle shape, an enclosing, a non-rectangular shape, or a line end shape, and wherein the estimate is generated by at least counting a number of polygons in the layer of the first anchor type.

15. The system of claim 12 , wherein the plurality of anchor types includes a 45° vertex or a 45° concave vertex, and wherein the estimate is generated by at least identifying non-orthogonal polygons in the layer and doubling the trapezoid number of the non-orthogonal polygons.

16. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
receive a first match time estimate associated with a first pattern anchor of a first anchor type of a plurality of anchor types within an integrated circuit (IC) pattern;
receive generate a second revised match time estimate associated with a second pattern anchor of a second anchor type of the plurality of anchor types within the IC pattern;
determine whether the first match time estimate is shorter than the second match time estimate;
in response to the first match time estimate being shorter than the second match time estimate, generate a plurality of target anchors of the first anchor type within a layer of a target IC layout; and
search the target IC layout for the IC pattern using the first pattern anchor and the plurality of target anchors.

17. The non-transitory computer readable medium of claim 16 , wherein the instructions, when executed by the processor, further cause the processor to:
generate an estimate of a number of target anchors of the first anchor type in the layer of the target IC layout;
calculate a ratio of the estimate to a number of candidate anchors of the first anchor type in the IC pattern;
revise the first match time by scaling the first match time estimate based on the ratio; and
revise the second match time.

18. The non-transitory computer readable medium of claim 17 , wherein the plurality of anchor types includes a vertex or a 90° concave vertex, and wherein the estimate is generated by at least counting a number of polygons in the layer.

19. The non-transitory computer readable medium of claim 17 , wherein the plurality of anchor types includes a rectangle shape, an enclosing, a non-rectangular shape, or a line end shape, and wherein the estimate is generated by at least counting a number of polygons in the layer of the first anchor type.

20. The non-transitory computer readable medium of claim 17 , wherein the plurality of anchor types includes a 45° vertex or a 45° concave vertex, and wherein the estimate is generated by at least identifying non-orthogonal polygons in the layer and doubling the trapezoid number of the non-orthogonal polygons.

Assignees

• Synopsys Inc

Inventors

• Gao Chen
• Xue Yuli
• Tan Tony
• Fang Weiping

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title