Dynamic load balancing and configuration management for heterogeneous compute accelerators in a data center

Patent metadata

Field	Value
Publication number	US-11487585-B1
Application number	US-201615379153-A
Country	US
Kind code	B1
Filing date	Dec 14, 2016
Priority date	Dec 14, 2016
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

An example method of managing a plurality of hardware accelerators in a computing system includes executing workload management software in the computing system configured to allocate a plurality of jobs in a job queue among a pool of resources in the computer system; monitoring the job queue to determine required hardware functionalities for the plurality of jobs; provisioning at least one hardware accelerator of the plurality of hardware accelerators to provide the required hardware functionalities; configuring a programmable device of each provisioned hardware accelerator to implement at least one of the required hardware functionalities; and notifying the workload management software that each provisioned hardware accelerator is an available resource in the pool of resources.

First claim

What is claimed is:

1. A method of managing a plurality of hardware accelerators in a computing system, comprising:
predictively provisioning a plurality of hardware accelerator boards from a pool of resources in the computing system by predicting hardware functionalities based on historical data and provisioning the plurality of hardware accelerator boards based on the predicted hardware functionalities, wherein each hardware accelerator board comprises one or more programmable devices and one or more hardware functionalities specific to the hardware accelerator board, wherein the one or more hardware functionalities satisfies the predicted hardware functionalities;
executing workload management software in the computing system configured to receive and allocate a plurality of jobs in a job queue to the plurality of provisioned hardware accelerator boards based on the one or more hardware functionalities of each of the plurality of provisioned hardware accelerator boards;
monitoring the job queue to determine whether a configuration of the one or more hardware functionalities of the plurality of provisioned hardware accelerator boards satisfies required hardware functionalities for the plurality of jobs;
in response to determining the configuration does not satisfy the required hardware functionalities, modifying the plurality of provisioned hardware accelerator boards to satisfy the required hardware functionalities for the plurality of jobs by provisioning at least one additional hardware accelerator board from the pool of resources to implement the required hardware functionalities, wherein the at least one additional hardware accelerator board was not predictively provisioned;
after provisioning the at least one additional hardware accelerator board, configuring the one or more programmable devices of each provisioned hardware accelerator board, as well as the at least one additional hardware accelerator board, to implement at least one of the required hardware functionalities;
after configuring the one or more programmable devices, notifying the workload management software that each provisioned hardware accelerator board is an available resource in the pool of resources for allocation of the plurality of jobs in the job queue; and
validating the configuration of the one or more programmable devices of each provisioned hardware accelerator board prior to the notifying the workload management software.

2. The method of claim 1 , wherein the computing system further comprises a plurality of free hardware accelerator boards not part of the pool of resources, and wherein modifying the plurality of provisioned hardware accelerator boards comprises:
determining that the pool of resources does not include an available hardware accelerator board that satisfies the required hardware functionalities; and
selecting at least one of the plurality of free hardware accelerator boards to provision into the plurality of provisioned hardware accelerator boards to provide the required hardware functionalities.

3. The method of claim 1 , wherein the configuring comprises:
removing at least one of the hardware accelerator boards from the pool of resources; and
reconfiguring the one or more programmable devices of each removed hardware accelerator board to implement at least one of the required hardware functionalities.

4. The method of claim 1 , wherein the configuring comprises:
loading a configuration bitstream to each provisioned hardware accelerator board selected from a plurality of configuration bitstreams.

5. The method of claim 1 , further comprising:
maintaining the historical data tracking the required hardware functionalities for the plurality of jobs over time.

6. A non-transitory computer-readable medium having instructions stored thereon, which when executed by a processor cause the processor to perform a method of managing a plurality of hardware accelerator boards in a computing system, comprising:
predictively provisioning the plurality of hardware accelerator boards from a pool of resources in the computing system by predicting hardware functionalities based on historical data and provisioning the plurality of hardware accelerator boards based on the predicted hardware functionalities, wherein each hardware accelerator board comprises one or more programmable devices and one or more hardware functionalities specific to the hardware accelerator board, wherein the one or more hardware functionalities satisfies the predicted hardware functionalities;
executing workload management software in the computing system configured to receive and allocate a plurality of jobs in a job queue to the plurality of provisioned hardware accelerator boards based on the one or more hardware functionalities of each of the plurality of provisioned hardware accelerator boards;
monitoring the job queue to determine whether a configuration of the one or more hardware functionalities of the plurality of provisioned hardware accelerator boards satisfies required hardware functionalities for the plurality of jobs;
in response to determining the configuration does not satisfy the required hardware functionalities, modifying the plurality of provisioned hardware accelerator boards to satisfy the required hardware functionalities for the plurality of jobs by provisioning at least one additional hardware accelerator board from the pool of resources to implement the required hardware functionalities, wherein the at least one additional hardware accelerator board was not predictively provisioned;
after provisioning the at least one additional hardware accelerator board, configuring the one or more programmable devices of each provisioned hardware accelerator boards, as well as the at least one additional hardware accelerator board, to implement at least one of the required hardware functionalities; and
after configuring the one or more programmable devices, notifying the workload management software that each provisioned hardware accelerator board is an available resource in the pool of resources for allocation of the plurality of jobs in the job queue; and
validating the configuration of the one or more programmable devices of each provisioned hardware accelerator board prior to the notifying the workload management software.

7. The non-transitory computer-readable medium of claim 6 , wherein the computing system further comprises a plurality of free hardware accelerator boards not part of the pool of resources, and wherein the modifying the plurality of provisioned hardware accelerator boards comprises:
determining that the pool of resources does not include an available hardware accelerator board that satisfies the required hardware functionalities; and
selecting at least one free hardware accelerator boards from the plurality of free hardware accelerator boards to provision into the plurality of provisioned hardware accelerator boards to provide the required hardware functionalities.

8. The non-transitory computer-readable medium of claim 6 , wherein the configuring comprises:
removing at least one of the hardware accelerator boards from the pool of resources; and
reconfiguring the one or more programmable devices of each removed hardware accelerator board to implement at least one of the required hardware functionalities.

9. The non-transitory computer-readable medium of claim 6 , wherein the configuring comprises:
loading a configuration bitstream to each provisioned hardware accelerator board selected from a plurality of configuration bitstreams.

10. The non-transitory computer-readable medium of claim 6 , further comprising:
maintaining the historical data tracking the required hardware functionalities for the plur

Assignees

• Xilinx Inc

Inventors

• Gilliland Spenser
• Mirkis Andrew
• Martinez Vallina Fernando J
• Kesavan Ambujavalli
• Allen Michael D

Classifications

• G06F9/5044 Primary

  considering hardware capabilities · CPC title

• G06F9/505 Primary

  considering the load · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F15/7889

  Reconfigurable logic implemented as a co-processor (instruction execution using a coprocessor G06F9/3877) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title