High accuracy low temperature drift high-side current sensing hardware and method

Patent metadata

Field	Value
Publication number	US-11486914-B2
Application number	US-202117492210-A
Country	US
Kind code	B2
Filing date	Oct 1, 2021
Priority date	Sep 18, 2020
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A circuit includes a tank capacitor coupled between first and second nodes, and a sense resistor having a first terminal coupled to the first node and a second terminal coupled to a regulator input. A switching circuit has first and second inputs coupled to the first and second terminals of the sense resistor. A gain stage has first and second inputs capacitively coupled to first and second outputs of the switching circuit. An analog-to-digital converter receives the output of the gain stage, and receives first and second differential voltages. A reference voltage generator has a temperature independent current source coupled to source current to a reference resistor, the first differential reference voltage being formed across the reference resistor. The reference resistor and sense resistor are located sufficiently close to one another on a single common substrate such that they remain at substantially a same temperature.

First claim

The invention claimed is:

1. A circuit, comprising:
a tank capacitor coupled between first and second nodes;
a sense resistor having a first terminal coupled to the first node and a second terminal coupled to a regulator input;
a switching circuit having first and second inputs respectively coupled to the first and second terminals of the sense resistor;
a gain stage having first and second inputs capacitively coupled to first and second outputs of the switching circuit;
an analog to digital converter (ADC) receiving the output of the gain stage, and first and second differential voltages; and
a reference voltage generator comprising a temperature independent current source coupled to source current to a reference resistor, wherein the first differential reference voltage is formed across the reference resistor;
wherein the reference resistor and sense resistor are located sufficiently close to one another on a single common substrate such that they remain at substantially a same temperature during operation.

2. The circuit of claim 1 , wherein the reference resistor surrounds at least a part of a perimeter of the sense resistor.

3. The circuit of claim 1 , wherein the reference resistor is formed by a plurality of supermodules distributed about opposite sides of a perimeter of the sense resistor.

4. The circuit of claim 3 , wherein each supermodule is comprised of a superstructure and an associated metal layer, with the superstructures of supermodules on a first side of the perimeter of the sense resistor having a same surface area as the superstructures of supermodules on a second side of the perimeter of the sense resistor, the second side being opposite the first side.

5. The circuit of claim 3 , wherein each supermodule is comprised of a superstructure and an associated metal layer; wherein the supermodules are distributed about the perimeter of the sense resistor such that the superstructure of each supermodule on the perimeter of a first side of the sense resistor is opposite to a superstructure of another supermodule on the perimeter of a second side of the sense resistor, the second side being opposite the first side.

6. The circuit of claim 5 , wherein the plurality of supermodules comprise first, second, third, and fourth supermodules, with the first and second supermodules being located on the perimeter of the first side of the sense resistor and the third and fourth supermodules being located on the perimeter of the second side of the sense resistor.

7. The circuit of claim 6 , wherein the first and second supermodules are arranged such that the superstructure of the first supermodule is adjacent the superstructure of the second supermodule but spaced apart from the metal layer of the second supermodule, and such that the superstructure of the second supermodule is adjacent the superstructure of the first supermodule but spaced apart from the metal layer of the first supermodule.

8. The circuit of claim 1 , wherein the reference resistor is separated into substructures spaced equally about a perimeter of the sense resistor.

9. The circuit of claim 1 , wherein the reference resistor and the sense resistor are formed by at least two different resistive materials and for which an amount of contribution of each material with respect to an overall value of a resistance that is a multiple of a resistance of the sense resistor is identical for both the reference resistor and the sense resistor.

10. The circuit of claim 1 , wherein the reference resistor and the sense resistor are formed from multiple resistive materials.

11. The circuit of claim 10 , wherein the multiple resistive materials of the reference resistor and sense resistor include part of each resistor being polysilicon and part of each resistor being metal.

12. The circuit of claim 1 , wherein the gain stage comprises:
a first amplifier having a first input coupled to the first output of the switching circuit by a first high voltage capacitor, a second input coupled to the second output of the switching circuit by a second high voltage capacitor, a first switch selectively coupling the first input of the first amplifier to a first output of the first amplifier, and a second switch selectively coupling the second input of the first amplifier to a second output of the first amplifier.

13. The circuit of claim 12 , wherein a common mode circuit couples a common mode voltage between the first and second outputs of the first amplifier.

14. The circuit of claim 12 , further comprising:
a second amplifier having a first input coupled to the first output of the first amplifier by a first low voltage capacitor, a second input coupled to the second output of the first amplifier by a second low voltage capacitor, a third switch selectively coupling the first input of the second amplifier to a first output of the second amplifier, and a fourth switch selectively coupling the second input of the second amplifier to a second output of the second amplifier.

15. The circuit of claim 14 , wherein a common mode circuit couples a common mode voltage between the first and second outputs of the first amplifier, and between the first and second outputs of the second amplifier.

16. A circuit, comprising:
a tank capacitor coupled between first and second nodes;
a sense resistor having a first terminal coupled to the first node and a second terminal coupled to a regulator input;
a switching circuit having first and second inputs respectively coupled to the first and second terminals of the sense resistor;
a gain stage having first and second inputs capacitively coupled to first and second outputs of the switching circuit;
an analog to digital converter (ADC) receiving the output of the gain stage, and first and second differential voltages; and
a reference voltage generator comprising a temperature independent current source coupled to source current to a reference resistor, wherein the first differential reference voltage is formed across the reference resistor;
wherein the switching circuit comprises:
a first switch selectively coupling the first input of the switching circuit to the first output of the switching circuit in response to a logical OR of first and second switch control signals;
a second switch selectively coupling the first input of the switching circuit to the second output of the switching circuit in response to a logical OR of the first switch control signal and a third switch control signal;
a third switch selectively coupling the second input of the switching circuit to the second output of the switching circuit in response to the second switch control signal; and
a fourth switch selectively coupling the second input of the switching circuit to the first output of the switching circuit in response to the third switch control signal.

17. The circuit of claim 16 , wherein the reference resistor surrounds at least a part of a perimeter of the sense resistor.

18. The circuit of claim 16 , wherein the reference resistor is formed by a plurality of supermodules distributed about opposite sides of a perimeter of the sense resistor.

19. The circuit of claim 18 , wherein each supermodule is comprised of a superstructure and an associated metal layer, with the superstructures of supermodules on a first side of the perimeter of the sense resistor having a same surface area as the superstructures of supermodules on a second side of the perimeter of the sense resistor, the second side being opposite the first side.

20. The circuit of claim 18 , whe

Assignees

• St Microelectronics Asia Pacific Pte Ltd

Inventors

• Guedon Yannick
• Yildirim Baris Volkan
• Lee Teerasak

Classifications

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• G01R27/02 Primary

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title

• H02J7/02

  for charging batteries from AC mains by converters · CPC title

• H02J50/12

  of the resonant type · CPC title

• H02J50/10

  using inductive coupling · CPC title