Direct conversion receiver using coherent integration

Patent metadata

Field	Value
Publication number	US-11483123-B2
Application number	US-202017020321-A
Country	US
Kind code	B2
Filing date	Sep 14, 2020
Priority date	Sep 13, 2019
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

A receiver includes a circuit designed to process, based on a plurality of timed waveform reference locations, a waveform signal, the waveform signal comprising a message. The circuit may include a clock source, an input configured to receive the waveform signal, a time location reference circuit coupled to the clock source, the time location reference circuit designed to output the plurality of timed waveform reference locations, each timed waveform reference location being set by the clock, and a signal processing circuit coupled to the time location reference circuit, the signal processing circuit designed to generate an output voltage in a response to the waveform signal being inputted into the signal processing circuit through the input and processed at each timed waveform reference location from the series of timed waveform reference locations. A transmitter that generates the waveform signal can be also provided where the clocks are matched.

First claim

What is claimed is:

1. A receiver comprising a circuit configured to process, based on a series of timed waveform reference locations, a waveform signal, the waveform signal comprising a message, wherein the circuit comprises:
a clock source;
an input configured to receive the waveform signal;
a time location reference circuit coupled to the clock source, the time location reference circuit configured to output the series of timed waveform reference locations, each timed waveform reference location from the series of timed waveform reference locations being set by the clock source; and
a signal processing circuit coupled to the time location reference circuit, the signal processing circuit configured to generate an output voltage in a response to the waveform signal being inputted into the signal processing circuit through the input and in a further response to the waveform signal being processed at the each timed waveform reference location from the series of timed waveform reference locations.

2. The receiver of claim 1 , further comprising a comparator configured to compare the output voltage with a threshold voltage.

3. The receiver of claim 1 , wherein the time location reference circuit comprises a field programmable gate array (FPGA).

4. The receiver of claim 1 , wherein the time location reference circuit comprises a bit-counter and a decoder.

5. The receiver of claim 1 , wherein the signal processing circuit comprises a plurality of voltage integrator circuits, each voltage integrator circuit from the plurality of voltage integrator circuits comprises a switch coupled to each of a respective timed waveform reference location and the input, a capacitor coupled to each of the switch and a ground to integrate at least one of a voltage and a current flowing through the switch from the input, and a diode.

6. The receiver of claim 5 , wherein the switch is a metal oxide semiconductor field effect transistor (MOSFET), wherein the respective timed waveform reference location is coupled to a gate terminal on the MOSFET, wherein the capacitor is coupled to a source terminal on the MOSFET and wherein the input is coupled to a drain terminal on the MOSFET.

7. The receiver of claim 1 , further comprising an amplifier disposed mediate the input and the signal processing circuit.

8. The receiver of claim 7 , further comprising a capacitor disposed mediate the amplifier and the signal processing circuit, the capacitor blocking a voltage flowing back to the amplifier.

9. The receiver of claim 8 , further comprising a resistor disposed mediate the capacitor and the signal processing circuit, the resistor limiting current flow into the capacitor.

10. The receiver of claim 9 , further comprising a voltage bias circuit.

11. The receiver of claim 1 , further comprising an indicator coupled to the signal processing circuit, the indicator being actuated when an output voltage is one of being equal to and exceeding a voltage required to actuate the indicator.

12. The receiver of claim 11 , further comprising an amplifier disposed between the signal processing circuit and the indicator.

13. The receiver of claim 1 , further comprising an antenna in a connection with the input, the antenna capturing the waveform signal transmitted through an atmospheric layer medium.

14. The receiver of claim 1 , further comprising a cable in a connection with the input, the cable carrying the waveform signal originated at a remote device.

15. The receiver of claim 1 , wherein the receiver configured to perform a form of a coherent integration at each timed waveform reference location respectively.

16. The receiver of claim 1 , wherein the receiver configured to perform a form of a coherent integration and a form of non-coherent integration at each timed waveform reference location respectively.

17. The receiver of claim 1 , wherein the circuit further comprises:
an amplifier disposed mediate the input and the signal processing circuit;
a capacitor disposed mediate the amplifier and the signal processing circuit, the capacitor blocking a current flow back to the amplifier;
a resistor disposed mediate the capacitor and the signal processing circuit, the resistor limiting the current flow into the capacitor; and
a voltage bias circuit.

18. The receiver of claim 1 , wherein the clock source comprises a chip scale atomic clock (CSAC), a rubidium atomic clock, a hydrogen MASER clock, a cesium atomic clock, a global positioning system (GPS) derived clock or a GPS disciplined clock.

19. A receiver comprising a circuit configured to process, based on a series of timed waveform reference locations, a waveform signal, the waveform signal comprising a message, wherein the circuit comprises:
a clock source;
an input configured to receive the waveform signal;
a time location reference circuit coupled to the clock source, the time location reference circuit configured to output the series of timed waveform reference locations, each timed waveform reference location from the series of timed waveform reference locations being set by the clock source;
a first signal processing circuit coupled to the time location reference circuit, the first signal processing circuit configured to generate a first voltage in a response to the waveform signal being inputted into the first signal processing circuit through the input and in a further response to the waveform signal being processed at the each timed waveform reference location from the series of timed waveform reference locations; and
a second signal processing circuit coupled to the time location reference circuit, the second signal processing circuit configured to generate a second voltage in a response to the waveform signal being inputted into the second signal processing circuit through the input and in a further response to the waveform signal being processed at the each timed waveform reference location from the series of timed waveform reference locations.

20. The receiver of claim 19 , further comprising:
a voltage subtractor circuit outputting a voltage difference between the first voltage and the second voltage; and
a comparator configured to compare the voltage difference with a threshold voltage.

21. The receiver of claim 20 , further comprising a voltage integrator disposed between the voltage subtractor circuit and the comparator.

22. A receiver comprising a circuit configured to process, based on a series of timed waveform reference locations, a waveform signal, the waveform signal comprising a message, wherein the circuit comprises:
a clock source;
an input configured to receive the waveform signal;
a time location reference circuit coupled to the clock source, the time location reference circuit configured to output the series of timed waveform reference locations, each timed waveform reference location from the series of timed waveform reference locations being set by the clock source;
a first circuit coupled to the time location reference circuit, the first circuit configured to generate a plurality of voltages in a response to the waveform signal being inputted into the first circuit through the input and in a further response to the waveform signal being processed at each timed waveform reference location from the series of timed waveform reference locations; and
a second circuit coupled to the first circuit, the second circuit configured to convert each voltage from the plurality of voltages from an analog form into a digital form.

Assignees

• Nokomis Inc

Inventors

• Chornenky Todd Eric

Classifications

• H04W56/0035 Primary

  detecting errors in frequency or phase · CPC title

• H04B1/16

  Circuits · CPC title

• H04L7/0037

  Delay of clock signal · CPC title

• H04B7/22

  Scatter propagation systems {, e.g. ionospheric, tropospheric or meteor scatter} · CPC title

• H04B17/336

  Signal-to-interference ratio [SIR] or carrier-to-interference ratio [CIR] · CPC title