Receiving circuit, and semiconductor apparatus and semiconductor system using the same

Patent metadata

Field	Value
Publication number	US-11482973-B2
Application number	US-202016941266-A
Country	US
Kind code	B2
Filing date	Jul 28, 2020
Priority date	Feb 10, 2020
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

A receiving circuit may include a first amplifying circuit, a second amplifying circuit, a third amplifying circuit, and a feedback circuit. The first amplifying circuit amplifies a first input signal and a second input signal to generate a first amplified signal and a second amplified signal, respectively. The second amplifying circuit amplifies the first amplified signal and the second amplified signal to generate a first preliminary output signal and a second preliminary output signal, respectively. The third amplifying circuit amplifies the first preliminary output signal and the second preliminary output signal to generate a first output signal and a second output signal, respectively. The feedback circuit changes voltage levels of the first amplified signal and the second amplified signal based on a current control signal, the first output signal, and the second output signal.

First claim

What is claimed is:

1. A receiving circuit comprising:
a first amplifying circuit configured to amplify a first input signal and a second input signal to generate a first amplified signal and a second amplified signal;
a second amplifying circuit configured to amplify the first amplified signal and the second amplified signal to generate a first preliminary output signal and a second preliminary output signal;
a third amplifying circuit configured to amplify the first preliminary output signal and the second preliminary output signal to generate a first output signal and a second output signal; and
a feedback circuit configured to change a voltage level of the first amplified signal based on the first output signal, change a voltage level of the second amplified signal based on the second output signal, and adjust variation widths of the voltage levels of the first amplified signal and the second amplified signal based on a current control signal.

2. The receiving circuit according to claim 1 , wherein, as the variation widths of the voltage levels increase according to the current control signal, bandwidths of the first amplified signal and the second amplified signal increase.

3. The receiving circuit according to claim 1 , wherein the feedback circuit comprises:
a first transistor configured to connect a first amplifying node, through which the first amplified signal is outputted, and a first node based on the first output signal;
a second transistor configured to connect a second amplifying node, through which the second amplified signal is outputted, and a second node based on the second output signal; and
a variable current circuit configured to discharge the first and second nodes based on the current control signal.

4. The receiving circuit according to claim 3 , wherein the feedback circuit further comprises:
a coupling circuit configured to connect the first and second nodes based on a switch control signal,
wherein, when the first and second nodes are connected through the coupling circuit, DC gains and bandwidths of the first amplified signal and the second amplified signal are increased and AC gains of the first amplified signal and the second amplified signal are decreased.

5. The receiving circuit according to claim 4 , wherein the coupling circuit comprises:
a resistor element connected between the first and second nodes;
a capacitor element connected in parallel with the resistor element between the first and second nodes; and
a switch configured to short-circuit the first and second nodes based on the switch control signal.

6. The receiving circuit according to claim 1 , wherein the third amplifying circuit comprises:
a variable load circuit connected between a third node, to which a first voltage is applied, and a first output node, through which the first output signal is outputted, connected between a fourth node, to which the first voltage is applied, and a second output node, through which the second output signal is outputted, and having a resistance value adjusted based on a resistance control signal;
a first input transistor connected between the first output node and a second voltage terminal and configured to change a voltage level of the first output node based on the second preliminary output signal; and
a second input transistor connected between the second output node and the second voltage terminal and configured to change a voltage level of the second output node based on the first preliminary output signal.

7. The receiving circuit according to claim 6 , wherein, as a resistance value of the variable load circuit increases based on the resistance control signal, a total gain of the first output signal and the second output signal increases.

8. The receiving circuit according to claim 6 , wherein the second amplifying circuit comprises:
a first load transistor configured to provide the first voltage to the first preliminary output node based on a voltage level of the fourth node, wherein the first preliminary output signal is outputted through the first preliminary output node;
a second load transistor configured to provide the first voltage to the second preliminary output node based on a voltage level of the third node, wherein the second preliminary output signal is outputted through the second preliminary output node;
a third input transistor connected between the first preliminary output node and the second voltage terminal and configured to change a voltage level of the first preliminary output node based on the second amplified signal; and
a fourth input transistor connected between the second preliminary output node and the second voltage terminal and configured to change a voltage level of the second preliminary output node based on the first amplified signal.

9. A receiving circuit comprising:
a first amplifying circuit configured to amplify a first input signal and a second input signal to generate a first amplified signal and a second amplified signal;
a second amplifying circuit configured to amplify the first amplified signal and the second amplified signal to generate a first preliminary output signal having a logic level corresponding to the first amplified signal and a second preliminary output signal having a logic level corresponding to the second amplified signal;
a third amplifying circuit configured to amplify the first preliminary output signal and the second preliminary output signal to generate a first output signal having a logic level corresponding to the first preliminary output signal and a second output signal having a logic level corresponding to the second preliminary output signal, and configured to increase a total gain of the first and second output signals based on a resistance control signal; and
a feedback circuit configured to change a voltage level of the first amplified signal based on the first output signal, configured to change a voltage level of the second amplified signal based on the second output signal, and configured to increase bandwidths of the first amplified signal and the second amplified signal based on a current control signal.

10. The receiving circuit according to claim 9 , wherein the feedback circuit is further configured to receive a switch control signal, increase DC gains and bandwidths of the first amplified signal and the second amplified signal, and decrease AC gains of the first amplified signal and the second amplified signal based on the switch control signal.

11. The receiving circuit according to claim 9 , wherein the feedback circuit comprises:
a first transistor configured to connect a first amplifying node, through which the first amplified signal is outputted, and a first node based on the first output signal;
a second transistor configured to connect a second amplifying node, through which the second amplified signal is outputted, and a second node based on the second output signal; and
a variable current circuit configured to discharge the first and second nodes based on the current control signal.

12. The receiving circuit according to claim 11 , wherein the feedback circuit further comprises:
a coupling circuit configured to connect the first and second nodes based on a switch control signal,
wherein, when the first and second nodes are connected through the coupling circuit, DC gains and bandwidths of the first amplified signal and the second amplified signal are increased and AC gains of the first amplified signal and the second amplified signal are decreased.

13. The receiving circuit according to claim 12 , wherein the coupling circuit comprises:
a resistor element connected between the first and second node

Assignees

• Sk Hynix Inc

Inventors

• Kang Ji Hyo

Classifications

• H03G3/3036 Primary

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title

• H03G1/0029

  using field-effect transistors [FET] · CPC title

• H03G1/0088

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F3/45197

  Pl types (H03F3/45224, H03F3/45251 take precedence) · CPC title