AC to DC converter with parallel converter

US11482944B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11482944-B2
Application numberUS-201816007731-A
CountryUS
Kind codeB2
Filing dateJun 13, 2018
Priority dateFeb 15, 2018
Publication dateOct 25, 2022
Grant dateOct 25, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus having an AC rectifier configured to generate one or more rectified signals from an alternating current (AC) signal, bus having a positive line and a negative line, parallel converter connected between the positive line and the negative line, and bulk capacitor coupled to the parallel converter. The bus is connected to the AC rectifier to receive a first of the rectified signals between the positive line and the negative line. The apparatus has a controller configured to operate the parallel converter in a first mode in which energy from a second of the rectified signals from the AC rectifier is stored in the bulk capacitor and a second mode in which the energy stored in the bulk capacitor is discharged to the bus to increase a voltage on the bus during at least an initial portion of the second mode.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: an AC rectifier configured to generate one or more rectified voltages from an alternating current (AC) voltage having a peak voltage each half cycle; a bus having a positive line and a negative line, wherein the bus is connected to the AC rectifier to receive a first of the one or more rectified voltages that is between the positive line and the negative line; a parallel converter connected between the positive line and the negative line of the bus, wherein the parallel converter is connected to the AC rectifier in order to receive a second of the one or more rectified voltages; a bulk capacitor coupled to the parallel converter, wherein the parallel converter further comprises a switch connected to a first terminal of the bulk capacitor, wherein a second terminal of the bulk capacitor is connected to the negative line of the bus; and a controller configured to operate the parallel converter in a first mode approximately twice each cycle of the AC voltage in which energy from the second of the one or more rectified voltages is stored in the bulk capacitor and a second mode approximately twice each cycle of the AC voltage in which the energy stored in the bulk capacitor is discharged to the bus to increase a voltage on the bus during at least an initial portion of the second mode, wherein the controller is further configured to operate the parallel converter in the first mode approximately twice each cycle of the AC voltage to transfer charge from the bus to the bulk capacitor to increase a voltage on the bulk capacitor to a greater magnitude than the peak AC voltage, wherein the controller is configured to control the switch in the second mode to use the energy stored in the bulk capacitor to increase the voltage on the bus and to maintain the voltage on the bus at or above a minimum specified bus voltage, wherein during the initial portion of the second mode the voltage on the bus is increased to a voltage having approximately the same magnitude as the magnitude of the voltage on the bulk capacitor, wherein the voltage on the bus is increased to greater than the peak voltage of the AC voltage approximately each half cycle. 2. The apparatus of claim 1 , wherein the controller is further configured to, approximately twice each cycle of the AC voltage, stop charging the bulk capacitor in the first mode and to start discharging the energy stored in the bulk capacitor to the bus in the second mode at or prior to the voltage on the bus dropping to the minimum specified bus voltage. 3. The apparatus of claim 1 , wherein the switch is a first switch, and further comprising a second switch connected between the inductor and the negative line of the bus, wherein the parallel converter is configured to operate the second switch in a boost mode during the first mode to store energy in the bulk capacitor using the rectified voltage from the AC rectifier. 4. The apparatus of claim 3 , wherein the parallel converter is configured to repeatedly open and close the first switch in a buck mode during an initial portion of the second mode to increase the voltage on the bus using the energy stored in the bulk capacitor. 5. The apparatus of claim 3 , wherein the parallel converter is configured to keep the first switch closed in a shorting mode throughout the second mode to increase the voltage on the bus using the energy stored in the bulk capacitor. 6. The apparatus of claim 1 , wherein the controller is further configured to: repeatedly open and close the switch in the parallel converter during a first phase of the second mode to increase the voltage on the bus using the energy stored in the bulk capacitor, wherein the first phase comprises the initial portion of the second mode; and close the switch to connect the bulk capacitor through the inductor to the positive line during a second phase of the second mode to maintain the voltage on the bus at or above the minimum specified bus voltage. 7. The apparatus of claim 1 , further comprising a voltage converter coupled between the bus and a DC output of the apparatus, wherein the voltage converter is configured to convert the voltage from the bus and provide the converted voltage to the DC output. 8. A method of operating an alternating current (AC) to direct current (DC) converter, the method comprising: receiving an AC voltage at an input of an AC rectifier in the AC to DC converter, the AC voltage having a peak voltage each half cycle; rectifying the AC voltage by the AC rectifier to produce one or more rectified voltages; providing a first of the one or more rectified voltages to a bus having a positive line and a negative line; controlling a parallel converter in a first mode approximately twice each cycle of the AC voltage and a second mode approximately twice each cycle of the AC voltage, including: using a second of the one or more rectified voltages during the first mode to store energy into a bulk capacitor coupled to the parallel converter and to increase a voltage on the bulk capacitor approximately twice each cycle of the AC voltage to a greater magnitude than the peak voltage of the AC voltage, wherein the parallel converter is connected between the positive line and the negative line of the bus, wherein the bulk capacitor has a first terminal connected to the negative line of the bus and a second terminal connected to a switch in the parallel converter; and discharging the energy stored in the bulk capacitor to the bus to increase the voltage on the bus during at least an initial portion of the second mode, including controlling the switch in the second mode to use the energy stored in the bulk capacitor to increase the voltage on the bus and to maintain the voltage on the bus at or above a minimum specified bus voltage, controlling the parallel converter in the second mode further comprising: operating the parallel converter in a buck mode during a first phase of the second mode to increase the voltage on the bus using energy stored in the bulk capacitor during the first mode; and keeping the switch on during a second phase of the second mode to maintain the voltage on the bus at or above the minimum specified bus voltage without operating the parallel converter in the buck mode. 9. The method of claim 8 , wherein controlling the parallel converter in the first mode further comprises stopping transferring charge from the bus to the bulk capacitor at or prior to the voltage on the bus dropping to a minimum specified voltage. 10. An alternating current (AC) to direct current (DC) converter comprising: a bus having a positive line and a negative line; an AC rectifier having an input having a first terminal and a second terminal, the AC rectifier having a negative output, a first positive output, and a second positive output, wherein the first positive output is connected to the positive line of the bus, wherein the negative output is connected to the negative line of the bus, wherein the AC rectifier is configured to rectify an AC voltage received at the input and to provide a first rectified voltage between the negative output and the first positive output and a second rectified voltage between the negative output and the second positive output, wherein the AC voltage has a peak voltage each half cycle; a parallel converter connected to the second positive output of the AC rectifier to receive the second rectified voltage from the AC rectifier, wherein the parallel converter has a first terminal connected to the positive line, a second terminal connected to the negative line, and a third terminal; an inductor having a first terminal connected to the second positive output of the AC rectifier and a second terminal; a b

Assignees

Inventors

Classifications

  • including plural semiconductor devices as final control devices for a single load · CPC title

  • H02M7/06Primary

    using discharge tubes without control electrode or semiconductor devices without control electrode · CPC title

  • H02M1/15Primary

    using active elements · CPC title

  • using semiconductor devices only · CPC title

  • Means for protecting converters other than automatic disconnection · CPC title

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What does patent US11482944B2 cover?
An apparatus having an AC rectifier configured to generate one or more rectified signals from an alternating current (AC) signal, bus having a positive line and a negative line, parallel converter connected between the positive line and the negative line, and bulk capacitor coupled to the parallel converter. The bus is connected to the AC rectifier to receive a first of the rectified signals be…
Who is the assignee on this patent?
Huawei Digital Power Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H02M7/06. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 25 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).