Method of forming a contact plug in a semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-11482452-B2
Application number	US-202017134101-A
Country	US
Kind code	B2
Filing date	Dec 24, 2020
Priority date	Dec 24, 2020
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

In a method of forming a contact plug in a semiconductor integrated circuit device, the contact plug may be formed in a process chamber of a substrate-processing apparatus. The process chamber may have a process space. The process chamber may include a substrate supporter placed in a lower region of the process space to support a semiconductor substrate, and a gas injector placed in an upper region of the process space to inject a gas to the semiconductor substrate. An insulating interlayer having a contact hole may be formed on the semiconductor substrate loaded into the process space. A nucleation layer may be formed on an inner surface of the contact hole and an upper surface of the insulating interlayer. A semi-bulk layer may be formed on the nucleation layer in a lower region of the contact hole. An inhibiting layer may be formed on the semi-bulk layer and the exposed nucleation layer. A main-bulk layer may be formed on the semi-bulk layer to fill the contact hole with the main-bulk layer.

First claim

What is claimed is:

1. A method of forming a contact plug in a semiconductor integrated circuit device, the method comprising:
providing a semiconductor substrate loaded into a process chamber, the semiconductor substrate including a first surface in which an insulating interlayer having a contact hole is formed and a second surface opposite to the first surface;
forming a nucleation layer on an inner surface of the contact hole and an upper surface of the insulating interlayer, the inner surface of the contact hole including a bottom surface, a lower sidewall extending from an edge of the bottom surface and an upper sidewall extending from the lower sidewall;
forming a semi-bulk layer on the nucleation layer to have a thickness enough not to block an entrance of the contact hole, wherein a thickness of the semi-bulk layer formed on the bottom surface is thicker than that of the semi-bulk layer formed on the lower sidewall;
forming an inhibiting layer on a selected portion of the semi-bulk layer and an exposed portion of the nucleation layer; and
forming a main bulk layer on the semi-bulk layer to fill the contact hole with the main bulk layer.

2. The method of claim 1 , wherein forming the nucleation layer comprises supplying a hydrogen source and a tungsten source by an atomic layer deposition (ALD) process.

3. The method of claim 1 , wherein forming the inhibiting layer comprises treating the semi-bulk layer on the upper sidewall of the contact hole and the upper surface of the insulating interlayer using nitrogen radicals by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process to react the nitrogen radicals with the semi-bulk layer.

4. The method of claim 1 , further comprising:
supplying an edge gas so as not to generate the inhibiting layer on the second surface of the semiconductor substrate.

5. The method of claim 4 , wherein the edge gas comprises an Ar gas.

6. The method of claim 1 , wherein the inhibiting layer comprises tungsten nitride.

7. The method of claim 1 , wherein forming the main bulk layer and forming the inhibiting layer are performed in the process chamber by an in-situ process.

8. The method of claim 1 , wherein forming the main bulk layer comprises reacting a nitrogen source with a tungsten source.

9. A method of forming a contact plug in a semiconductor integrated circuit device, the method comprising:
forming an insulating interlayer having a contact hole on a first surface of a semiconductor substrate;
forming a tungsten nucleation layer on an inner surface of the contact hole and an upper surface of the insulating interlayer, the inner surface of the contact hole;
forming a semi-tungsten layer on the tungsten nucleation layer, to have uneven thicknesses;
treating the semi-tungsten layer and the exposed tungsten nucleation layer using nitrogen radicals to form an inhibiting layer;
forming a main tungsten layer on the semi-tungsten layer, the tungsten nucleation layer and the inhibiting layer to fill the contact hole with the main bulk layer; and
planarizing the main tungsten layer, the inhibiting layer and the tungsten nucleation layer to expose the upper surface of the insulating interlayer;
wherein the semi-tungsten layer has a thickness for allowing an entrance of the contact hole to be exposed, and
wherein a deposition rate of the main tungsten layer of an upper region of the contact hole is lowered compared to a deposition rate of a lower region of the contact hole.

10. The method of claim 9 , further comprising:
supplying an edge gas so as not to generate the inhibiting layer on a second surface of the semiconductor substrate, the second surface being opposite to the first surface.

11. The method of claim 10 , wherein the edge gas comprises an Ar gas.

Assignees

• Wonik Ips Co Ltd

Inventors

• Yoon Won Jun
• Sun Woo Hoon
• Choi Seok Kyu
• Han Tae Sung
• Kim Dong Woo
• Park Jin Wu

Classifications

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/045 Primary

  for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD] · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/076

  in via holes or trenches · CPC title