Ceramic electronic component and manufacturing method of the same

US11482379B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11482379-B2
Application numberUS-202017089559-A
CountryUS
Kind codeB2
Filing dateNov 4, 2020
Priority dateNov 18, 2019
Publication dateOct 25, 2022
Grant dateOct 25, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A ceramic electronic component includes a multilayer chip including a multilayer structure and cover layers disposed on top and bottom faces in a stack direction of the multilayer structure, and a pair of external electrodes respectively formed on two edge faces of the multilayer structure and extending to four side faces of the multilayer chip, wherein each external electrode has a recessed portion on at least one of two side faces facing each other in the stack direction or at least one of remaining two side faces, and wherein each external electrode has no recessed portion on the two side faces when each external electrode has the recessed portion on at least one of the remaining two side faces, and has no recessed portion on the remaining two side faces when each external electrode has the recessed portion on at least one of the two side faces.

First claim

Opening claim text (preview).

What is claimed is: 1. A ceramic electronic component comprising: a multilayer chip having a substantially rectangular parallelepiped shape and including a multilayer structure and cover layers disposed on a top face and a bottom face in a stack direction of the multilayer structure, the multilayer structure including dielectric layers and internal electrode layers that are alternately stacked, the dielectric layers being mainly composed of ceramic, the internal electrode layers being alternately exposed to two edge faces of the multilayer structure facing each other; and a pair of external electrodes respectively formed on the two edge faces, each external electrode extending to four side faces of the multilayer chip, wherein each external electrode has a recessed portion on at least one of two side faces facing each other in the stack direction or at least one of remaining two side faces, wherein each external electrode has no recessed portion on the two side faces when each external electrode has the recessed portion on at least one of the remaining two side faces, and has no recessed portion on the remaining two side faces when each external electrode has the recessed portion on at least one of the two side faces, wherein when each external electrode has the recessed portion on at least one of the remaining two side faces, the at least one of the remaining two side faces is not exposed from each external electrode in the recessed portion, and when each external electrode has the recessed portion on at least one of the two side faces, the at least one of the two side faces is not exposed from each external electrode in the recessed portion, and wherein the recessed portion is located within a region sandwiched between the two edge faces and between the two side faces as viewed from above in a first direction in which the remaining two side faces face each other and is not located outside the region sandwiched between the two edge faces and between the two side faces as viewed from above in the first direction when each external electrode has the recessed portion on at least one of the remaining two side faces, and is located within a region sandwiched between the two edge faces and between the remaining two side faces as viewed from above in a second direction in which the two side faces face each other and is not located outside the region sandwiched between the two edge faces and between the remaining two side faces as viewed from above in the second direction when each external electrode has the recessed portion on at least one of the two side faces. 2. The ceramic electronic component according to claim 1 , wherein each external electrode has the recessed portion on at least one of the two side faces facing each other in the stack direction and has no recessed portion on the remaining two side faces. 3. The ceramic electronic component according to claim 1 , wherein each external electrode has the recessed portion on at least one of the remaining two side faces and has no recessed portion on the two side faces facing each other in the stack direction. 4. The ceramic electronic component according to claim 1 , wherein a recess level X expressed by X=d t is 25% or greater and 75% or less, where t represents a distance between a center of a straight line and a side face of the multilayer chip on which the external electrode has the recessed portion, the straight line connecting a first point with a second point, the first point being a point farthest from the side face of the multilayer chip on which the external electrode has the recessed portion in an outer edge of the recessed portion, the second point being a point closest to the side face of the multilayer chip on which the external electrode has the recessed portion in the outer edge of the recessed portion, and d represents a distance between the center and a point at which the recessed portion is deepest. 5. The ceramic electronic component according to claim 1 , wherein a face on which the recessed portion is formed is to be a mounting surface to a circuit board. 6. The ceramic electronic component according to claim 1 , further comprising: a covering portion covering five faces excluding a face on which the recessed portion is formed among six faces of the ceramic electronic component. 7. A manufacturing method of a ceramic electronic component comprising: alternately stacking dielectric green sheets for ceramic dielectric layers and conductive pastes for internal electrode layers so that the internal electrode layers are alternately exposed to two edge faces facing each other and disposing a cover sheet on an uppermost layer and another cover sheet on a lowermost layer so as to form a ceramic multilayer structure having a substantially rectangular parallelepiped shape; applying a metal paste on each of the two edge faces of the ceramic multilayer structure in a manner such that the metal paste extends to four side faces of the ceramic multilayer structure; forming a recessed portion in the metal paste on at least one of two side faces facing each other in a first direction perpendicular to a second direction and a third direction so that the at least one of the two side faces is not exposed from the metal paste in the recessed portion and the recessed portion is located within a region sandwiched between the two edge faces and between remaining two side faces facing each other in the second direction as viewed from above in the first direction and is not located outside the region sandwiched between the two edge faces and between the remaining two side faces as viewed from above in the first direction, and forming no recessed portion in the metal paste on the remaining two side faces, the second direction being a stack direction of the ceramic multilayer structure, the third direction being a facing direction of the two edge faces; and firing the metal paste and the ceramic multilayer structure simultaneously. 8. The manufacturing method according to claim 7 , wherein a density of the cover sheet and a density of the another cover sheet are less than a density of the dielectric green sheet. 9. A manufacturing method of a ceramic electronic component comprising: alternately stacking dielectric green sheets for ceramic dielectric layers and conductive pastes for internal electrode layers to form a multilayer structure; disposing cover sheets respectively on a top face and a bottom face in a stack direction of the multilayer structure; forming two edge faces to which the internal electrode layers are alternately exposed and two side faces to which the internal electrode layers are all exposed by cutting the multilayer structure; disposing a side margin sheet on each of the two side faces to which all the internal electrode layers are exposed to form a ceramic multilayer structure having a substantially rectangular parallelepiped shape, the conductive pastes for internal electrode layers being alternately exposed to two edge faces facing each other of the ceramic multilayer structure; applying a metal paste on each of the two edge faces of the ceramic multilayer structure in a manner such that the metal past extends to four side faces of the ceramic multilayer structure; forming a recessed portion in the metal paste on at least one of two side faces facing each other in the stack direction so that the at least one of the two side faces is not exposed from the metal paste in the recessed portion and the recessed portion is located within a region sandwiched between the two edge faces and between side faces other than the two side faces among the four side faces as viewed from above in the stack direction and is not located outside the region sandwiched between the two edge fac

Assignees

Inventors

Classifications

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

  • Manufacturing or production processes characterised by the final manufactured product · CPC title

  • Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00 · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

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What does patent US11482379B2 cover?
A ceramic electronic component includes a multilayer chip including a multilayer structure and cover layers disposed on top and bottom faces in a stack direction of the multilayer structure, and a pair of external electrodes respectively formed on two edge faces of the multilayer structure and extending to four side faces of the multilayer chip, wherein each external electrode has a recessed po…
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 25 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).