Residence time measurement for traffic engineered network

US11477100B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11477100-B2
Application numberUS-201715716110-A
CountryUS
Kind codeB2
Filing dateSep 26, 2017
Priority dateSep 26, 2017
Publication dateOct 18, 2022
Grant dateOct 18, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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Residence time is a variable part of the propagation delay of the packet. Information about the propagation delay for each transient node can be used as performance metric to calculate the Traffic Engineered route that can conform to delay and delay variation requirements. In an exemplary embodiment, a computing device uses special test packets to measure residence time. The computing device calculates routes to direct special test packets to one or more nodes. A node may calculate the residence time metric, such as a residence time variation (RTV), or residence time (RT) per ordered set of ingress and egress interfaces of the node. The computing device may also collect the residence time metric per test set from each node and may use this information to calculate the Test Engineered route.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of packet communication, comprising: receiving, by a plurality of nodes within a network domain, a test packet configured to traverse the plurality of nodes according to a list included in the test packet, wherein the list comprises an ordered set of ingress interface identifiers and egress interface identifiers of the plurality of nodes, wherein the ordered set indicates an order to be traversed by the test packet, wherein the list comprises, for each node of the plurality of nodes, a first identifier that is immediately followed by a second identifier that is different from the first identifier, wherein the first identifier uniquely identifies a node within the network domain and the second identifier identifies another node adjacent to the node, and wherein, for a first node and a second node from the plurality of nodes, the list includes a same second identifier that identifies a third node and a fourth node that are respectively adjacent to the first node and the second node; identifying, by each of the plurality of nodes, information indicative of a requested residence time measurement for the test packet; reading, by each of the plurality of nodes, a first clock value as the test packet is passed thereto; reading, by each of the plurality of nodes, a second clock value as the test packet is passed therefrom; calculating, by each of the plurality of nodes, a residence time of the test packet as a function of the first clock value and the second clock value; and transmitting, by each of the plurality of nodes to a computing device, a residence time report comprising a test sequence number that identifies the test packet, a timestamp when the residence time report is transmitted by a node, the first identifier of the node, the residence time of the test packet, and an ingress interface identifier and an egress interface identifier associated with the node. 2. The method of claim 1 , wherein the calculating of the residence time of the test packet further includes calculating by subtracting the first clock value from the second clock value. 3. The method of claim 1 , wherein the list of the plurality of nodes to be traversed by the test packet is received from the computing device. 4. The method of claim 1 , wherein the list includes a plurality of node segment identifications (SIDs). 5. The method of claim 1 , wherein the list further comprises one or more adjacency segment identifications (Adj-SIDs). 6. The method of claim 1 , wherein the list includes an Explicit Route Object (ERO) that includes internet protocol addresses of the plurality of nodes. 7. The method of claim 1 , wherein the list is a Multi-Protocol Label Switching (MPLS) label stack. 8. A packet communication apparatus comprising: at least one processor and a memory having instructions stored thereon, wherein the instructions upon execution by the at least one processor configures the packet communication apparatus to: receive a test packet configured to traverse a plurality of nodes according to a list included in the test packet, wherein the list comprises an ordered set of ingress interface identifiers and egress interface identifiers of the plurality of nodes, wherein the ordered set indicates an order to be traversed by the test packet, wherein the list comprises, for each node of the plurality of nodes, a first identifier that is immediately followed by a second identifier that is different from the first identifier, wherein the first identifier uniquely identifies a node within the network domain and the second identifier identifies another node adjacent to the node, and wherein, for a first node and a second node from the plurality of nodes, the list includes a same second identifier that identifies a third node and a fourth node that are respectively adjacent to the first node and the second node; identify information indicative of a requested residence time measurement for the test packet; read a first clock value as the test packet is passed thereto; read a second clock value as the test packet is passed therefrom; calculate a residence time of the test packet as a function of the first clock value and the second clock value; and transmit, to a computing device a residence time report comprising a test sequence number that identifies the test packet, a timestamp when the residence time report is transmitted by a node, the first identifier of the node, the residence time of the test packet, and an ingress interface identifier and an egress interface identifier associated with the node. 9. The packet communication apparatus of claim 8 , wherein the at least one processor configures the packet communication apparatus to calculate the residence time of the test packet by subtracting the first clock value from the second clock value. 10. The packet communication apparatus of claim 8 , wherein the list includes a plurality of node segment identifications (SIDs). 11. The packet communication apparatus of claim 8 , wherein the list further comprises one or more adjacency segment identifications (Adj-SIDs). 12. The packet communication apparatus of claim 8 , wherein the list includes an Explicit Route Object (ERO) that includes internet protocol addresses of the plurality of nodes. 13. A computer platform configured to generate the list in claim 8 . 14. A non-transitory computer program product comprising a computer-readable medium having code stored thereon, the code, when executed by a processor, causing the processor to implement a method, the code comprising: instruction for receiving a test packet configured to traverse the plurality of nodes according to a list included in the test packet, wherein the list comprises an ordered set of ingress interface identifiers and egress interface identifiers of the plurality of nodes, wherein the ordered set indicates an order to be traversed by the test packet, wherein the list comprises, for each node of the plurality of nodes, a first identifier that is immediately followed by a second identifier that is different from the first identifier, wherein the first identifier uniquely identifies a node within the network domain and the second identifier identifies another node adjacent to the node, and wherein, for a first node and a second node from the plurality of nodes, the list includes a same second identifier that identifies a third node and a fourth node that are respectively adjacent to the first node and the second node; instruction for identifying information indicative of a requested residence time measurement for the test packet; instruction for reading a first clock value as the test packet is passed thereto; instruction for reading a second clock value as the test packet is passed therefrom; instruction for calculating a residence time of the test packet as a function of the first clock value and the second clock value; and instruction for transmitting, to a computing device, a residence time report comprising a test sequence number that identifies the test packet, a timestamp when the residence time report is transmitted by a node, the first identifier of the node, the residence time of the test packet, and an ingress interface identifier and an egress interface identifier associated with the node. 15. The non-transitory computer program product of claim 14 , wherein the instruction for calculating of the residence time of the test packet further includes instruction for calculating by subtracting the first clock value from the second clock value. 16. The non-transitory computer program product of

Assignees

Inventors

Classifications

  • Route discovery packet · CPC title

  • using time related information in packets, e.g. by adding timestamps · CPC title

  • Testing arrangements · CPC title

  • Delays · CPC title

  • using label swapping, e.g. multi-protocol label switch [MPLS] · CPC title

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What does patent US11477100B2 cover?
Residence time is a variable part of the propagation delay of the packet. Information about the propagation delay for each transient node can be used as performance metric to calculate the Traffic Engineered route that can conform to delay and delay variation requirements. In an exemplary embodiment, a computing device uses special test packets to measure residence time. The computing device ca…
Who is the assignee on this patent?
Zte Corp
What technology area does this patent fall under?
Primary CPC classification H04L43/0852. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 18 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).