Oscillating circuit and electronic device

Patent metadata

Field	Value
Publication number	US-11476803-B2
Application number	US-202017616642-A
Country	US
Kind code	B2
Filing date	Jan 7, 2020
Priority date	Jun 4, 2019
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents, and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sensor system.

First claim

What is claimed is:

1. An oscillating circuit, comprising: a capacitor charging and discharging circuit unit, a voltage comparison circuit unit, and a threshold voltage generation circuit unit;
wherein the capacitor charging and discharging circuit unit comprises a variable current source, negative current mirrors, positive current mirrors, a first switching transistor, a second switching transistor, and a capacitor, wherein the variable current source provides a variable current, the capacitor is grounded at one end and connected to a first node at the other end; the negative current mirrors and the first switching transistor mirror the variable current to the first node to charge the capacitor; the positive current mirrors and the second switching transistor mirror the variable current to the first node to discharge the capacitor; a control terminal of the first switching transistor and a control terminal of the second switching transistor are coupled, and the control terminal of the first switching transistor and the control terminal of the second switching transistor are connected to a second node;
wherein the voltage comparison circuit unit compares and amplifies a voltage difference between a third node and the first node and converts it into a single-ended signal; the single-ended signal is connected to the threshold voltage generation circuit unit, and regulates and controls an output voltage at an output of the threshold voltage generation circuit unit, the output of the threshold voltage generation circuit unit being connected to the third node; the single-ended signal is inverted and connected to the second node; one of the first switching transistor and the second switching transistor is cyclically and alternately turned on, causing the capacitor to be periodically charged and discharged, resulting a sawtooth wave voltage at the first node.

2. The oscillating circuit according to claim 1 , wherein the capacitor charging and discharging circuit unit comprises a first positive current mirror, a second positive current mirror, and a first negative current mirror, wherein an input of the first positive current mirror is connected to the variable current source, an output of the first positive current mirror is connected to an input of the first negative current mirror, an output of the first negative current mirror is connected to an input of the first switching transistor, an output of the first switching transistor is connected to the first node; an input of the second positive current mirror is connected to the variable current source, an output of the second positive current mirror is connected to an output of the second switching transistor, an input of the second switching transistor is connected to the first node.

3. The oscillating circuit according to claim 2 , wherein the capacitor charging and discharging circuit unit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, wherein the first NMOS transistor has a grounded source, the first NMOS transistor has a drain connected to the variable current source, and a gate of the first NMOS transistor is coupled to the drain of the first NMOS transistor;
wherein the second NMOS transistor has a grounded source and a gate connected to the gate of the first NMOS transistor, the second NMOS transistor has a drain connected to a drain of the first PMOS transistor; the first PMOS transistor has a source connected to an operating voltage, the first PMOS transistor has a gate coupled to the drain of the first PMOS transistor; the second PMOS transistor has a source connected to the operating voltage, a gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, and a drain of the second PMOS transistor is connected to a source of the third PMOS transistor; a gate of the third PMOS transistor is connected to the second node, and a drain of the third PMOS transistor is connected to the first node;
wherein the third NMOS transistor has its source grounded, the third NMOS transistor has its gate connected to the gate of the first NMOS transistor, the third NMOS transistor has its drain connected to a source of the fourth NMOS transistor; the fourth NMOS transistor has its gate connected to the second node, the fourth NMOS transistor has its drain connected to the first node;
wherein the first NMOS transistor and the second NMOS transistor form the first positive current mirror to mirror the variable current to the second NMOS transistor, causing the variable current to flow through the first PMOS transistor simultaneously; the first PMOS transistor and the second PMOS transistor form the first negative current mirror to mirror the variable current to the second PMOS transistor, the variable current reaches the first node through the third PMOS transistor, and the third PMOS transistor acts as the first switching transistor; the first NMOS transistor and the third NMOS transistor forming the second positive current mirror, mirroring the variable current to the third NMOS transistor, the variable current reaches the first node through the fourth NMOS transistor, and the fourth NMOS transistor acts as the second switching transistor.

4. The oscillating circuit according to claim 3 , wherein the second NMOS transistor and the first NMOS transistor have a same width-to-length ratio, the third NMOS transistor and the first NMOS transistor have a same width-to-length ratio, and the second PMOS transistor and the first PMOS transistor have a same width-to-length ratio.

5. The oscillating circuit according to claim 3 , wherein the voltage comparison circuit unit comprises a differential amplifier and a differential to single-ended circuit unit, the differential amplifier compares and amplifies a voltage difference between the third node and the first node and outputs at a fourth node and a fifth node, the first node is a positive phase terminal with respect to the fifth node, the third node is a positive phase terminal with respect to the fourth node; the differential to single-ended circuit unit amplifies a voltage difference between the fourth node and the fifth node and converts it into the single-ended signal for output at a sixth node.

6. The oscillating circuit according to claim 5 , wherein the differential amplifier comprises a fifth NMOS transistor, a sixth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a first tail current source, and the fourth PMOS transistor and the fifth PMOS transistor form a differential pair;
wherein the fourth PMOS transistor has a source connected to the first tail current source, the fourth PMOS transistor has a gate connected to the first node, the fourth PMOS transistor has a drain connected to the fourth node; the fifth NMOS transistor has a drain connected to the fourth node, the fifth NMOS transistor has a gate coupled to its drain, and the fifth NMOS transistor has a source grounded;
wherein the fifth PMOS transistor has a source connected to the first tail current source, the fifth PMOS transistor has a gate connected to the third node, the fifth PMOS transistor has a drain connected to the fifth node; the sixth NMOS transistor has a drain connected to the fifth node, the sixth NMOS transistor has a gate coupled to its drain, the sixth NMOS transistor has a source grounded.

7. The oscillating circuit according to claim 6 , wherein the differential to single-ended circuit unit comprises a seventh NMOS transistor, an eighth NMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor;
wherein the sixth PMOS transistor has a source connected to the operating voltage, the sixth PMOS transistor has its gate and dr

Assignees

• No 24 Research Institute Of China Electronics Tech Group Corporation
• Chongqing Gigachip Tech Co Ltd

Inventors

• Hu Rongbin
• Yi Ziqiang
• Zhou Gang
• Tang Dong
• Tang Ning
• Xu Daiguo
• Wang Jianan
• Chen Guangbing
• Fu Dongbing

Classifications

• H03B5/26

  frequency-determining element being part of bridge circuit in closed ring around which signal is transmitted; frequency-determining element being connected via a bridge circuit to such a closed ring, e.g. Wien-Bridge oscillator, parallel-T oscillator · CPC title

• H03B5/1271

  the frequency being controlled by a control current, i.e. current controlled oscillators · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03B2201/0266

  the means comprising a transistor · CPC title

• H03B5/1228

  the amplifier comprising one or more field effect transistors · CPC title