Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11476360-B2
Application number	US-202017025213-A
Country	US
Kind code	B2
Filing date	Sep 18, 2020
Priority date	Mar 20, 2018
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an inversion type semiconductor element that includes:
a substrate having a first conductivity type or a second conductivity type and made of semiconductor;
a first conductivity type layer formed on the substrate and made of a semiconductor having the first conductivity type with an impurity concentration lower than an impurity concentration of the substrate;
a second conductivity type region that is formed on the first conductivity type layer, and is made of a semiconductor having the second conductivity type;
a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed, and has, at least, a striped shape when the JFET portion is viewed from a normal direction of the substrate;
a source region that is formed on the second conductivity region, and is made of a semiconductor having the first conductivity type and a concentration higher than a concentration of the first conductivity type layer;
a gate insulation film formed on a channel region that is a part of the second conductivity type region;
a gate electrode formed on the gate insulation film;
an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole;
a source electrode electrically connected to the source region through the contact hole; and
a drain electrode formed on a back side of the substrate, forms the channel region by applying a gate voltage to the gate electrode and applying a voltage at a normal operation as a drain voltage to the drain electrode, and causes a current to flow between the source electrode and the drain electrode through the source region and the JFET portion,

wherein:
when the voltage at the normal operation is applied as the drain voltage, the JFET portion causes the current to flow while suppressing an extension amount of a depletion layer extending from the second conductivity type region;
when a voltage higher than the voltage at the normal voltage is applied as the drain voltage, the JFET portion is pinched off by the depletion layer; and
when a width at the linear portion in the JFET portion is defined as W, a first conductivity type impurity concentration of the JFET portion is defined as Nd, a second type impurity concentration of a portion sandwiching the JFET portion in the second conductivity type region is defined as Na, an elementary charge is defined as q, and a dielectric constant of the semiconductor is defined as ε, a mathematical expression of 90 [V]>(q×Nd×(Na+Nd)×W 2 )/2εNa is satisfied.

2. The semiconductor device according to claim 1 , wherein:
the second conductivity type region includes
a deep layer formed on the first conductivity type layer,
a base region that is connected to the source electrode and includes the channel region, and
a connection layer that is formed on the deep layer, connects the deep layer and the base region, and has the second conductivity type;

a current dispersion layer that has a width wider than a width of the JFET portion and the first conductivity type and is formed on the deep layer and the JFET portion;
the base region is formed on the current dispersion layer;
when the voltage at the normal operation is applied as the drain voltage, the current flows through the JFET portion and the current dispersion layer; and
when the drain voltage becomes higher than the voltage at the normal operation, the JFET portion is pinched off earlier than the current dispersion layer.

3. The semiconductor device according to claim 2 , wherein:
a high concentration layer is formed between the JFET portion and the first conductivity type layer and between the second conductivity type region and the first conductivity type layer, has an impurity concentration higher than an impurity concentration of the first conductive type layer, and has the first conductivity type.

4. The semiconductor device according to claim 2 , wherein:
a gate trench that penetrates the source region and the base region and reaches the current dispersion layer is formed;
a trench gate structure is configured by forming the gate insulation film and the gate electrode inside the gate trench; and
the width at the linear portion in the JFET portion is smaller than a width of the gate trench.

5. The semiconductor device according to claim 4 , wherein:
the trench gate structure includes a plurality of trench gate structures;
the plurality of trench gate structures are formed in a stripe shape by setting one direction of each of the plurality of trench gate structures to a longitudinal direction and extending; and
the JFET portion is formed in a strip shape in which the linear portion extends in the longitudinal direction of the trench gate structure.

6. The semiconductor device according to claim 4 , wherein:
the trench gate structure includes a plurality of trench gate structures;
the plurality of trench gate structures are formed in a stripe shape by setting one direction of each of the plurality of trench gate structures to a longitudinal direction and extending in the longitudinal direction;
the JFET portion includes a plurality of JFET portions;
a direction intersecting with the longitudinal direction of the trench gate structure is a longitudinal direction of each of the plurality of JFET portions; and
the plurality of JFET portions extend in the longitudinal direction.

7. The semiconductor device according to claim 1 , wherein:
the width at the linear portion in the JFET portion is 0.3 μm or less.

8. The semiconductor device according to claim 1 , wherein:
the semiconductor is a wide band gap semiconductor.

9. A method for manufacturing a semiconductor device, comprising:
preparing a substrate made of semiconductor having a first conductivity type or a second conductivity type;
forming a first conductivity type layer, made of a semiconductor having the first conductivity type with an impurity concentration lower than an impurity concentration of the substrate, on the substrate;
forming a deep layer, made of a semiconductor having the second conductivity type, on the first conductivity type layer;
forming a JFET portion on the first conductivity type layer, wherein the JFET portion is sandwiched by the deep layer and has, at least, a linear portion when the JFET portion is viewed from a normal direction of the substrate;
forming the current dispersion layer on the deep layer and the JFET portion, wherein a width of the current dispersion layer is wider than a width of the JFET portion, and the current dispersion layer is connected to the JFET portion;
forming a connection layer, made of a semiconductor having the second conductivity type, on the deep layer, wherein the JFET portion is connected to the deep layer;
forming a base region, made of a semiconductor having the second conductivity type, on the current dispersion layer and the connection layer, wherein the base region is connected to the connection layer;
forming a source region on the base region, wherein the source region is made of a semiconductor having the first conductivity type and a concentration higher than a concentration of the first conductivity type layer;
forming a gate insulation film on a channel region that is a part of the base region;
forming a gate electrode on the gate insulation film;
forming an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole;
forming a source electrode electrically connected to the source region through the contact hole;
forming a drain electrode on a back side of the substrate,
wherein:
due to the forming the JFET portio

Assignees

• Denso Corp

Inventors

• Ebihara Yasuhiro
• Takeuchi Yuichi
• Takaya Hidefumi
• Watanabe Yukihiro

Classifications

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title