Semiconductor device structure comprising source and drain protective circuits against electrostatic discharge (ESD)

Patent metadata

Field	Value
Publication number	US-11476207-B2
Application number	US-201916661377-A
Country	US
Kind code	B2
Filing date	Oct 23, 2019
Priority date	Oct 23, 2019
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a semiconductor substrate;
a gate disposed on the semiconductor substrate and extending in a first direction;
a source doped region disposed in the semiconductor substrate and extending in the first direction;
a drain doped region disposed in the semiconductor substrate and extending in the first direction, wherein the source doped region and the drain doped region are located on two opposite sides of the gate;
a plurality of source contact windows disposed on the source doped region and extending in the first direction;
a plurality of drain contact windows disposed on the drain doped region and extending in the first direction, wherein the drain contact windows and the source contact windows are in different rows from a top view;
a plurality of source conductive holes disposed on the source doped region;
a plurality of drain conductive holes disposed on the drain doped region, wherein the source conductive holes and the drain conductive holes are in different rows from the top view, wherein the source contact windows and the source conductive holes are alternately disposed along the first direction from the top view; and
a first source conductive element disposed on the source contact windows, wherein the first source conductive element is electrically connected to the source doped region and extends in the first direction.

2. The semiconductor device structure as claimed in claim 1 , further comprising:
a first drain conductive element disposed on the drain contact windows, wherein the first drain conductive element is electrically connected to the drain doped region and extends in the first direction.

3. The semiconductor device structure as claimed in claim 2 , wherein from a side perspective view, the first drain conductive element partially overlaps the first source conductive elements.

4. The semiconductor device structure as claimed in claim 2 , wherein the first drain conductive element offsets the first source conductive element.

5. The semiconductor device structure as claimed in claim 1 , wherein the first source conductive element is in physical contact with at least two source contact windows.

6. The semiconductor device structure as claimed in claim 1 , wherein the source conductive holes offset the source conductive windows.

7. The semiconductor device structure as claimed in claim 1 , wherein the first source conductive element is in physical contact with at least two source conductive holes.

8. The semiconductor device structure as claimed in claim 1 , further comprising:
a second source conductive element covering the first source conductive element and extending in the first direction.

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Lee Jian-Hsing
• Huang Shao-Chang
• Lin Chih-Hsuan
• Wang yu-kai
• Nidhi Karuna
• Chiou Hwa-Chyi

Classifications

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H01L29/41725

  Electricity · mapped topic