On-chip resistor trimming to compensate for process variation

Patent metadata

Field	Value
Publication number	US-11476018-B2
Application number	US-202117385625-A
Country	US
Kind code	B2
Filing date	Jul 26, 2021
Priority date	Nov 19, 2018
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

An amplifier receives an input and a feedback. A first transistor controlled by the amplifier output is coupled between a supply node and the feedback. A second transistor controlled by the amplifier output is coupled to the supply node and generates a bias current. A trimmed resistor coupled between the feedback and ground includes, for trimming resolution of N-bits, where X+Y=N: M resistors, where M=2X−1, each having a resistance equal to R*(2Y)*i, i being an index having a value ranging from 1 to 2X−1, a first of the M resistors having a resistance of R*2Y, a last of the M resistors having a resistance of R*2Y*(2X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

First claim

The invention claimed is:

1. A voltage to current converter, comprising:
an amplifier having an inverting terminal receiving an input voltage, a non-inverting terminal coupled to a feedback node, and an output;
a first transistor having a source coupled to a supply node, a drain coupled to the feedback node, and a gate coupled to the output of the amplifier;
a second transistor having a source coupled to the supply node, a drain generating a bias current, and a gate coupled to the output of the amplifier; and
a trimmed resistor coupled between the feedback node and ground, wherein the trimmed resistor comprises:
for a trimming resolution of N bits, where X+Y=N:
a first resistive circuit comprising:
M resistors, where M=2 X −1, with each of the M resistors having a resistance that is equal to R*(2 Y )*i, with i being an index having a value ranging from 1 to 2 X −1, such that a first of the M resistors has a resistance of R*2 Y , such that a second of the M resistors has a resistance of R*2 Y *2, such that a third of the M resistors has a resistance of R*2 Y *3, and such that a last of the M resistors has a resistance of R*2 Y *(2 X −1);
M switches respectively associated with the M resistors;
wherein each of the M resistors is directly electrically coupled between a first node and its associated one of the M switches; and
wherein each of the M switches selectively couples its associated one of the M resistors to a second node; and

a second resistive circuit comprising:
P resistors, where P=2 Y −1, with each of the P resistors having a resistance that is equal to R*i, such that a first of the P resistors has a resistance equal to R, such that a last of the P resistors has a resistance equal to R*(2 Y −1);
P switches respectively associated with the P resistors;
wherein each of the P resistors is directly electrically coupled between the second node and its associated one of the P switches; and
wherein each of the P switches selectively couples its associated one of the P resistors to a third node.

2. The voltage to current converter of claim 1 , wherein X and Y are equal.

3. The voltage to current converter of claim 1 , where N is 6, X is 3, and Y is 3.

4. The voltage to current converter of claim 1 , wherein M is equal to P.

5. A voltage to current converter, comprising:
an amplifier having an inverting terminal receiving an input voltage, a non-inverting terminal coupled to a feedback node, and an output;
a first transistor having a source coupled to a supply node, a drain coupled to the feedback node, and a gate coupled to the output of the amplifier;
a second transistor having a source coupled to the supply node, a drain generating a bias current, and a gate coupled to the output of the amplifier; and
a trimmed resistor coupled between the feedback node and ground, wherein the trimmed resistor comprises:
a first resistive network comprising:
M resistors having resistances which increase in multiple of a fixed number Q=2 Y in resistance value by R, such that a first of the M resistors has a resistance of R*Q=R*2 Y , with each subsequent one of the M resistors increasing in value by a multiple of Q, such that the Mth resistor has a resistance of R*Q*M=R*2 Y *M;
M switches respectively associated with the M resistors;
wherein each of the M resistors is directly electrically coupled between a first node and its associated one of the M switches; and
wherein each of the M switches selectively couples its associated one of the M resistors to a second node; and

a second resistive network comprising:
P resistors having resistances which increase linearly in resistance value by R, such that a first of the P resistors has a resistance value of R, with each subsequent one of the P resistors increasing in value by R such that the Pth resistor of the P resistors has a resistance value of R*P, wherein P=Q−1;
P switches respectively associated with the P resistors;
wherein each of the P resistors is directly electrically coupled between the second node and its associated one of the P switches; and
wherein each of the P switches selectively couples its associated one of the P resistors to a third node.

6. The voltage to current converter of claim 5 , further comprising a fixed resistor coupled between the feedback node and the first node, and a ground coupled to the third node.

7. The voltage to current converter of claim 5 , further comprising an (M+1)th switch directly electrically coupled between the first and second nodes, and an (P+1)th switch directly electrically coupled between the second node and the third node.

8. The voltage to current converter circuit of claim 5 , wherein Q is 8 and R is a unit resistance for setting trimming precision.

9. The voltage to current converter of claim 5 , wherein M is equal to P.

10. A voltage to current converter, comprising:
an amplifier having an inverting terminal receiving an input voltage, a non-inverting terminal coupled to a feedback node, and an output;
a first transistor having a source coupled to a supply node, a drain coupled to the feedback node, and a gate coupled to the output of the amplifier;
a second transistor having a source coupled to the supply node, a drain generating a bias current, and a gate coupled to the output of the amplifier; and
a trimmed resistor coupled between the feedback node and ground, wherein the trimmed resistor comprises:
for a trimming resolution of N bits, where X+Y=N:
a resistive circuit comprising:
M resistors, where M=2 X −1, with each of the M resistors having a resistance that is equal to R*(2 Y )*i, with i being an index having a value ranging from 1 to 2 X −1, such that a first of the M resistors has a resistance of R*2 Y , such that a second of the M resistors has a resistance of R*2 Y *2, such that a third of the M resistors has a resistance of R*2 Y *3, and such that a last of the M resistors has a resistance of R*2 Y *(2 X −1);
M switches respectively associated with the M resistors;
wherein each of the M resistors is directly electrically coupled between a first node and its associated one of the M switches; and
wherein each of the M switches selectively couples its associated one of the M resistors to a second node.

11. The voltage to current converter of claim 10 , wherein X and Y are equal.

12. The voltage to current converter of claim 10 , where N is 6, X is 3, and Y is 3.

13. A voltage to current converter, comprising:
an amplifier having an inverting terminal receiving an input voltage, a non-inverting terminal coupled to a feedback node, and an output;
a first transistor having a source coupled to a supply node, a drain coupled to the feedback node, and a gate coupled to the output of the amplifier;
a second transistor having a source coupled to the supply node, a drain generating a bias current, and a gate coupled to the output of the amplifier; and
a trimmed resistor coupled between the feedback node and ground, wherein the trimmed resistor comprises:
a resistive network comprising:
M resistors having resistances which increase in multiple of a fixed number Q=2 Y in resistance value by R, such that a first of the M resistors has a resistance of R*Q=R*2 Y , with each subsequent one of the M resistors increasing in value by a multiple of Q, such that the Mth resistor has a resistance of R*Q*M=R*2 Y *M;
M switches respectively associated with the M resistors;
wherein each of the M resistors is directly electrically coupled between a first node and its associated one of the M switches; and
wherein each of the M switches selectively couples its associated one of the M resistors to a second node.

Assignees

• St Microelectronics Int Nv

Inventors

• Kaushik Mohit
• Kumar Anil

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H01C10/16

  including plural resistive elements · CPC title

• H01C17/267 Primary

  by passage of voltage pulses or electric current · CPC title

• H01C1/16

  Resistor networks not otherwise provided for · CPC title

• H01C13/02 Primary

  Structural combinations of resistors · CPC title