Semiconductor device and designing method of semiconductor device
US-2015365089-A1 · Dec 17, 2015 · US
US11475196B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11475196-B2 |
| Application number | US-201716097185-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 30, 2017 |
| Priority date | Aug 14, 2017 |
| Publication date | Oct 18, 2022 |
| Grant date | Oct 18, 2022 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
It is provided an encryption hybrid model SI simulation method based on an ADS and an HSPICE. The method includes: extracting step response data of a TX end chip encryption model by using HSPICE transient simulation; externally generating a random code signal; and taking the extracted step response data and the random code signal as input sources of ADS channel simulation, to realize active simulation to the encryption hybrid model.
Opening claim text (preview).
The invention claimed is: 1. An encryption hybrid model signal integrity (SI) simulation method based on an Advance Design System (ADS) and an HSPICE, performed by an SI simulation device, the method comprising: extracting step response data of a transmitter (TX) end chip encryption model by using HSPICE transient simulation; externally generating a random code signal; and performing ADS channel simulation by taking the extracted step response data and the random code signal as input sources of the ADS channel simulation, to realize active simulation to the encryption hybrid model, wherein the HSPICE transient simulation comprises: reserving a model input interface in the TX end chip encryption model; building a wiring model required in a link; connecting the TX end chip encryption model and the wiring model, and providing the connected model in butt joint with a resistor; inputting an ideal step signal at the model input interface reserved in the TX end chip encryption model; and extracting the step response data at a position where the butt joint is provided. 2. The encryption hybrid model SI simulation method based on the ADS and the HSPICE according to claim 1 , wherein the step response data is a step response output file with a suffix of and a format of the step response output file is edited to make the step response output file to be a file with a suffix of .tim that is capable of being called by the ADS. 3. The encryption hybrid model SI simulation method based on the ADS and the HSPICE according to claim 1 , further comprising: transforming the wiring model into an S parameter for the ADS to call. 4. The encryption hybrid model SI simulation method based on the ADS and the HSPICE according to claim 3 , further comprising: transforming the wiring model into an S parameter for the ADS to call.
Circuit design at the analogue level · CPC title
based on channel impulse response [CIR] · CPC title
Providing cryptographic facilities or services · CPC title
File encryption · CPC title
Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.