Methods of determining operating conditions of silicon carbide power MOSFET devices associated with aging, related circuits and computer program products

Patent metadata

Field	Value
Publication number	US-11474145-B2
Application number	US-202016897719-A
Country	US
Kind code	B2
Filing date	Jun 10, 2020
Priority date	Jun 18, 2019
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

First claim

What is claimed is:

1. A method of operating a SiC MOSFET, the method comprising:
applying a first voltage across a gate-source junction of the SiC MOSFET to enable conduction of current predominantly through a reverse body diode of the SiC MOSFET rather than through a channel region of the SiC MOSFET;
conducting a first current into a source terminal of the SiC MOSFET through the reverse body diode to a drain terminal of the SiC MOSFET responsive to the first voltage;
determining a first drain-source voltage resulting from conducting the first current through the reverse body diode;
applying a second voltage across the gate-source junction to enable conduction of current predominantly through the channel region rather than through the reverse body diode;
determining a second drain-source voltage resulting from conducting current through the channel region responsive to the second voltage;
determining an indication of contact resistance of the SiC MOSFET as a function of aging of the SiC MOSFET using the first drain-source voltage; and
determining an indication of a degradation of a gate oxide of the SiC MOSFET as the function of aging of the SiC MOSFET using the second drain-source voltage.

2. The method according to claim 1 wherein applying the first voltage across the gate-source junction disables conduction of current through the channel region of the SiC MOSFET.

3. The method according to claim 2 wherein applying the second voltage across the gate-source junction disables conduction of the current through the reverse body diode of the SiC MOSFET.

4. The method according to claim 1 further comprising:
conducting a second current into the source terminal of the SiC MOSFET through the channel region to a drain terminal after determining the first drain-source voltage, wherein the first current is greater than the second current.

5. The method according to claim 1 further comprising:
electrically decoupling the source terminal, a gate terminal and a drain terminal from an application circuit in which the SiC MOSFET is included before applying the first voltage across the gate-source junction of the SiC MOSFET; and
electrically coupling the source terminal, the gate terminal and the drain terminal to the application circuit after determining the second drain-source voltage.

6. The method according to claim 5 further comprising:
allowing sufficient time for junction temperatures in the SiC MOSFET to reach a repeatable level before applying the first voltage and the second voltage across the gate-source junction.

7. The method according to claim 3 wherein the source terminal, a gate terminal and a drain terminal remain electrically coupled to an application circuit in which the SiC MOSFET is included while determining the first drain-source voltage and the second drain-source voltage.

8. The method according to claim 7 wherein determining the first drain-source voltage is performed responsive to detecting that the conduction of the current through the channel region is disabled and/or detecting that the conduction of the current through the reverse body diode is enabled; and
wherein determining the second drain-source voltage is performed responsive to detecting that the conduction of the current through the channel region is enabled and/or detecting that the conduction of the current through the reverse body diode is disabled.

9. The method according to claim 1 wherein operations of applying the first voltage, conducting the first current, determining the first drain-source voltage, applying the second voltage, and determining the second drain-source voltage are repeated periodically to provide the indication of the degradation of the gate oxide of the SiC MOSFET as the function of aging of the SiC MOSFET and the indication of the contact resistance of the SiC MOSFET as the function of aging of the SiC MOSFET.

10. The method of claim 1 wherein the first current conducted through the reverse body diode is at least about 95% of the current applied to the source terminal of the SiC MOSFET and a remainder of the current applied to the source terminal of the SiC MOSFET is conducted through the channel region of the SiC MOSFET.

11. The method of claim 1 wherein a magnitude of the first current is selected to be sufficient to detect an increase in a contact resistance variation of the SiC MOSFET as a function of aging of the SiC MOSFET.

12. The method of claim 4 wherein a magnitude of the second current is selected to be sufficient to detect an increase in a gate threshold voltage variation without a substantial effect due to a contact resistance of the SiC MOSFET as a function of aging of the SiC MOSFET.

13. The method according to claim 1 further comprising:
electrically decoupling the source terminal, a gate terminal and a drain terminal from an application circuit in which the SiC MOSFET is included before applying the first voltage across the gate-source junction of the SiC MOSFET; and
electrically coupling the source terminal, the gate terminal and the drain terminal to the application circuit after determining the second drain-source voltage.

14. A SiC MOSFET test circuit comprising:
a variable voltage circuit selectively coupled across a gate-source junction of a SiC MOSFET, the variable voltage circuit configured to provide a first voltage to disable conduction of current through a channel region of the SiC MOSFET and to enable conduction of current through a reverse body diode of the SiC MOSFET and configured to provide a second voltage across the gate-source junction to enable conduction of current through the channel region rather than through the reverse body diode;
a current circuit selectively coupled between a drain terminal of the SiC MOSFET and a source terminal of the SiC MOSFET, the current circuit configured to provide a first current into the source terminal through the reverse body diode to the drain terminal; and
a drain-source voltage detector circuit electrically coupled across the drain terminal and the source terminal, the drain-source voltage detector circuit configured to detect a first drain-source voltage generated responsive to the first voltage and configured to detect a second drain-source voltage generated responsive to the second voltage,
wherein operations of the test circuit are repeated periodically to provide an indication of a degradation of a gate oxide of the SiC MOSFET as a function of aging and an indication of contact resistance of the SiC MOSFET as the function of aging based on the first drain-source voltage and second drain-source voltage.

15. The circuit of claim 14 wherein the current circuit is configured to provide a second current into the source terminal through the channel region to the drain terminal after determining the first drain-source voltage, wherein the first current is greater than the second current.

16. The circuit of claim 15 further comprising:
an application circuit selectively coupled to a gate terminal, the drain terminal, and the source terminal, wherein the application circuit is configured to operate using the SiC MOSFET in an operating mode; and
a switch configured to electrically decouple the source terminal, the gate terminal and the drain terminal from the application circuit in which the SiC MOSFET is included before applying the first voltage across the gate-source junction of the SiC MOSFET in a test mode and is configured to electrically couple the source terminal, the gate terminal and the drain terminal to the application circuit after determining the second drain-source voltage.

Assignees

• Univ Texas

Inventors

• Ugur Enes
• Akin Bilal
• Yang Fei
• Pu Shi
• Xu Chi

Classifications

• G01R31/2642 Primary

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/2601

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

• G01R31/2644

  Adaptations of individual semiconductor devices to facilitate the testing thereof · CPC title