Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus

Patent metadata

Field	Value
Publication number	US-11469770-B2
Application number	US-202117163493-A
Country	US
Kind code	B2
Filing date	Jan 31, 2021
Priority date	Jan 31, 2021
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

First claim

We claim:

1. Multiplier-accumulator (MAC) with Analog to Digital Converter (ADC) comprising:
a differential charge transfer bus comprising a plurality of weighted positive charge transfer lines and a plurality of weighted negative charge transfer lines;
a first plurality of unit elements (UEs) configured as multiply-accumulate MAC UEs performing multiply-accumulate operations on respective X and W digital inputs, each MAC UE providing a multiplication result as a charge transferred to the differential charge transfer bus;
a second plurality of unit elements (UEs) configured as Bias UEs, each Bias UE having a bias digital input and coupled to the differential charge transfer bus, each Bias UE placing a bias value as a charge onto the differential charge transfer bus according to the bias digital input;
a third plurality of unit elements configured as ADC UEs arranged in a binary sequence of ADC UE groups, at least one subsequent group of ADC UEs having twice the number of ADC UEs as a previous group of ADC UEs, each ADC UE operative to convert a charge present on the differential charge transfer bus into a digital output value;
a charge combiner coupled to the differential charge transfer bus and generating a combined charge value to a comparator, the comparator generating a comparison output;
a successive approximation register (SAR) controller coupled to the comparison output and to a plurality of registers, each register coupled to a corresponding group of SAR-UEs and causing each corresponding group of SAR UEs to transfer or remove charge on the differential charge transfer bus until a number of bits equal to a number of registers in the plurality of registers has shifted through the plurality of registers, thereby generating a digital MAC output.

2. The MAC with ADC of claim 1 where the positive charge transfer lines and negative charge transfer lines are each nine in number and have respective weights of 1, 2, 4, 2, 4, 8, 4, 8, and 16.

3. The MAC with ADC of claim 2 where a sum of the first plurality of UEs configured as MAC UEs, the second plurality of UEs configured as Bias UEs, and the third plurality of UEs configured as ADC UEs is approximately 766.

4. The MAC with ADC of claim 1 where the charge combiner comprises a positive charge combiner and a negative charge combiner, each positive charge combiner and negative charge combiner comprising capacitors, each capacitor having a first terminal connected to a respective positive charge transfer line or negative charge transfer line, and a second terminal summed to a second terminal of other capacitors of the charge combiner.

5. The MAC with ADC of claim 4 where, for a scaling factor Cs equal to or greater than a smallest value of a charge transfer capacitor of a MAC UE or Bias UE coupled to a charge transfer line, a charge transfer line with weight 1 has a summing capacitor value of approximately 8 Cs, a charge transfer line with weight 2 has a summing capacitor value of approximately 16 Cs, a charge transfer line with weight 4 has a summing capacitor value of approximately 33 Cs, a charge transfer line with weight 8 has a summing capacitor value of approximately 69 Cs, and a charge transfer line with weight 16 has a summing capacitor value of approximately 152 Cs.

6. The MAC with ADC of claim 1 where each MAC UE, Bias UE, and ADC UE is configured to have associated digital input bits coupled to NAND gates, each NAND gate configured to generate a positive output and a negative output, the positive output coupled through a charge transfer capacitor to a respective positive charge transfer line, and the negative output coupled through a charge transfer capacitor to a respective negative charge transfer line.

7. The MAC with ADC of claim 1 where each MAC UE is coupled to the differential charge transfer bus, each MAC UE receiving a respective X digital input and a respective W digital input which includes a sign bit, each MAC UE comprising a positive MAC UE and a negative MAC UE, each positive MAC UE and negative MAC UE comprising:
a plurality of NAND-groups equal to a total number of W digital input bits, each NAND-group comprising a plurality of NAND gates, each NAND gate of a NAND-group having one input commonly coupled to a W digital input bit, one input coupled to a unique one of the X digital input bits, and either the sign bit or an inverted said sign bit, each NAND gate generating a positive output and a negative output;
each NAND gate positive output and each NAND gate negative output coupled through a charge transfer capacitor to a unique charge transfer line of the differential charge transfer bus.

8. The MAC with ADC of claim 7 where a NAND gate which is enabled when the sign bit is not asserted has a respective positive output coupled through a respective charge transfer capacitor to a negative charge transfer line and a respective negative output coupled through a respective charge transfer capacitor to a positive charge transfer line.

9. The MAC with ADC of claim 7 where a NAND gate which is enabled when the sign bit is asserted has a respective positive output coupled through a respective charge transfer capacitor to a positive charge transfer line and a respective negative output coupled through a respective charge transfer capacitor to a negative charge transfer line.

10. A multiplier-accumulator (MAC) with Analog to Digital Converter (ADC) comprising:
a differential charge transfer bus comprising a plurality of weighted positive charge transfer lines and a plurality of weighted negative charge transfer lines;
a first plurality of unit elements configured as MAC UEs coupled to the differential charge transfer bus and each MAC UE configured to have a digital X input and a digital W input;
a second plurality of unit elements configured as Bias UEs coupled to the differential charge transfer bus and configured to have a digital E input;
a third plurality of unit elements configured as ADC UEs coupled to the differential charge transfer bus and configured to convert a charge coupled to the differential charge transfer bus into a digital output value;
where at least one of a MAC UE or a Bias UE has an input coupled to a NAND gate generating an output and an inverted output, each of the output and the inverted output coupled through a charge transfer capacitor to the differential charge transfer bus.

11. The MAC with ADC of claim 10 wherein at least one MAC UE of the first plurality of MAC UEs comprises:
NAND-groups equal in number to a number of bits of the W input, each NAND-group comprising NAND gates equal in number to a number of bits of the X input, each NAND gate in a NAND-group having an input coupled to one of the W input bits and having an input coupled to a unique one of the X input bits.

12. The MAC with ADC of claim 10 wherein at least one Bias UE of the second plurality of Bias UEs comprises a plurality of NAND gates, each NAND gate generating an output and an inverted output, each output coupled to a positive charge transfer line and each inverted output coupled to a negative charge transfer line.

13. The MAC with ADC of claim 10 wherein at least one ADC UE of said plurality of ADC UEs comprises a plurality of NAND gates generating an output and an inverted output, each output coupled to a one of the weighted positive charge transfer lines and each inverted output coupled to one of the weighted a negative charge transfer lines, said plurality of ADC UEs transferring and removing charge from the differential charge transfer bus in a binary sequence of successive approximation, the ADC UEs having inputs coupled to a controller which switches ADC UEs according to a sum

Assignees

• Redpine Signals Inc
• Ceremorphic Inc

Inventors

• Kraemer Martin
• Boesch Ryan
• Xiong Wei

Classifications

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• G06F2207/4814

  Non-logic devices, e.g. operational amplifiers · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• H03M3/04 Primary

  Differential modulation with several bits {, e.g. differential pulse code modulation [DPCM] (H03M3/30 takes precedence)} · CPC title