Systems, methods, and devices for digital-to-analog conversion in data transmission

Patent metadata

Field	Value
Publication number	US-11469768-B2
Application number	US-202117188696-A
Country	US
Kind code	B2
Filing date	Mar 1, 2021
Priority date	Mar 1, 2021
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

First claim

What is claimed is:

1. A digital to analog converter (DAC), comprising:
a first amplifier that receives a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block;
a first filter circuit that filters the first signal, the first filter circuit including a first capacitance;
an output that outputs an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block; and
a second filter circuit that filters the second signal, the second filter circuit including a second capacitance separate from the first capacitance, wherein the output outputs the analog signal based on the filtered first signal and the filtered second signal.

2. The DAC of claim 1 , further comprising:
a second amplifier that receives the second bit of the data block as an input and output the second signal to the second filter circuit based on the value of the second bit of the data block.

3. The DAC of claim 2 , wherein the first filter circuit further includes a first resistance, wherein the second filter circuit further includes a second resistance, and wherein the first filter circuit passively filters the first signal and the second filter circuit passively filters the second signal.

4. The DAC of claim 3 , wherein the first bit is a less significant bit of the data block than the second bit, and wherein a first value of the first resistance is greater than a second value of the second resistance.

5. The DAC of claim 4 , wherein a first value of the first capacitance is less than a second value of the second capacitance.

6. The DAC of claim 5 , wherein a gain of the second amplifier is greater than a gain of the first amplifier.

7. The DAC of claim 6 , wherein the gain of the second amplifier is at least twice the gain of the first amplifier.

8. The DAC of claim 7 , wherein the first resistance and the first capacitance are connected in parallel, and wherein the second resistance and the second capacitance are connected in parallel.

9. The DAC of claim 3 , further comprising:
a third resistance connected between an output of the first amplifier and the first filter circuit; and
a fourth resistance connected between an output of the second amplifier and the second filter circuit.

10. The DAC of claim 3 , wherein values of the first and second resistances and values of the first and second capacitances are selected such that the first and second filter circuits have a substantially same frequency response for the filtered first and second signals.

11. The DAC of claim 3 , further comprising:
circuitry that adjusts values of at least one of the second resistance or the second capacitance.

12. A transmitter, comprising:
a parallel input serial output (PISO) device that outputs digital serialized data based on digital parallel input data; and
a digital to analog (DAC) converter including:
a first amplifier that receives a first bit of a data block in the digital serialized data as an input and output a first signal based on a value of the first bit;
a first filter circuit that filters the first signal, the first filter circuit including a first capacitance;
a second amplifier that receives a second bit of the data block as an input and output a second signal based on a value of the second bit;
a second filter circuit that filters the second signal, the second filter circuit including a second capacitance separate from the first capacitance; and
an output that outputs an analog signal based on the filtered first and second signals.

13. The transmitter of claim 12 , wherein the first filter circuit includes a first passive filter including the first capacitance, and the second filter circuit includes a second passive filter including the second capacitance.

14. The transmitter of claim 12 , further comprising:
a first signal generator that generates a first clock signal for the PISO device; and
a second signal generator that generates a second clock signal for the DAC.

15. The transmitter of claim 14 , wherein a frequency of the first clock signal is less than a frequency of the second clock signal.

16. The transmitter of claim 12 , further comprising:
an electrostatic discharge device coupled to the output of the DAC and a node that connects to a load.

17. A digital to analog converter (DAC), comprising:
a plurality of branches, at least one branch including:
a driver including an input and an output, the input of the driver being connected to a respective node that receives a signal that represents a respective bit in a data block;
a filter including an input and an output, the input of the filter being connected to the output of the driver; and

an output commonly connected to the plurality of branches and that outputs an analog signal, wherein, for the at least one branch, the filter includes a first resistance connected in parallel with a capacitance.

18. The DAC of claim 17 , wherein a number of the plurality of branches is based on a number of bits in the data block.

19. The DAC of claim 17 , wherein the at least one branch further comprises:
a second resistance connected between the output of the driver and the input of the filter.

20. The DAC of claim 17 , wherein the driver includes an amplifier, and wherein the amplifier for each branch in the plurality of branches has a different gain.

Assignees

• Mellanox Technologies Ltd

Inventors

• Kushnir Igal
• Gordon Eshel
• Levi Roi

Classifications

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H04B1/04 Primary

  Circuits · CPC title

• H03M1/78

  using ladder network · CPC title

• H03M1/808

  using resistors · CPC title