Display panel, method of manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-11469291-B2
Application number	US-201917040846-A
Country	US
Kind code	B2
Filing date	Nov 29, 2019
Priority date	Nov 29, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A display substrate includes a substrate and a plurality of sub-pixels arranged in an array on the substrate. The sub-pixel includes: a data line pattern extending along a first direction; a power signal line pattern, the power signal line pattern including a portion extending along the first direction: and a sub-pixel driving circuit. The sub-pixel driving circuit includes two switching transistors, a driving transistor, and a storage capacitor; a first/second electrode plate of the storage capacitor is coupled to a gate electrode of the driving transistor/ the power signal line pattern, second electrodes of the two switching transistors are both coupled to a first electrode of the driving transistor, and orthographic projection of a second electrode of at least one of the two switching transistors on the substrate at least partially overlaps orthographic projection of the power signal line pattern or the second electrode plate on the substrate.

First claim

What is claimed is:

1. A display substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; wherein the sub-pixel comprises:
a data line pattern extending along a first direction;
a power signal line pattern, the power signal line pattern including a portion extending along the first direction;
a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes two switching transistors, a driving transistor, and a storage capacitor; a first electrode plate of the storage capacitor is coupled to a gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is coupled to the power signal line pattern; second electrodes of the two switching transistors are both coupled to a first electrode of the driving transistor, and an orthographic projection of a second electrode of at least one of the two switching transistors on the substrate at least partially overlaps an orthographic projection of the power signal line pattern on the substrate, and at least partially overlaps an orthographic projection of the second electrode plate of the storage capacitor on the substrate,
wherein the display substrate further includes a shielding component, at least part of the shielding component extends along the first direction,
wherein the second electrodes of the two switching transistors and the first electrode of the driving transistor are an integral structure, and the integral structure includes a first conductive portion extending in the first direction, an orthographic projection of the first conductive portion on the substrate, the orthographic projection of the power signal line pattern on the substrate, and the orthographic projection of the second electrode plate of the storage capacitor on the substrate have a first overlapping region, and the first overlapping region does not overlap an orthographic projection of the data line pattern on the substrate.

2. The display substrate according to claim 1 , wherein an orthographic projection of the first electrode of the driving transistor on the substrate is located in the orthographic projection of the second electrode plate of the storage capacitor on the substrate.

3. The display substrate according to claim 1 , wherein the sub-pixel further comprises: a gate line pattern and a light emitting control signal line pattern both extending along a second direction, the second direction intersecting the first direction;
the sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switching transistors include a fourth transistor and a fifth transistor;
a gate electrode of the fourth transistor is coupled to the gate line pattern, a first electrode of the fourth transistor is coupled to the data line pattern, and a second electrode of the fourth transistor is coupled to a second electrode of the fifth transistor, a gate electrode of the fifth transistor is coupled to the light emitting control signal line pattern, and a first electrode of the fifth transistor is coupled to the power signal line pattern;
a gate electrode of the first transistor is coupled to the gate line pattern, a second electrode of the first transistor is coupled to the gate electrode of the driving transistor, the first electrode of the first transistor, a first electrode of the six transistor and the second electrode of the driving transistor are formed as an integral structure, and the integral structure includes a second conductive portion extending along the first direction, a gate electrode of the sixth transistor is coupled to the light emitting control signal line pattern, and a second electrode of the sixth transistor is coupled to the light emitting element in the sub-pixel;
an orthographic projection of a channel region of the driving transistor on the substrate is located between an orthographic projection of the first conductive portion on the substrate and an orthographic projection of the second conductive portion on the substrate; and along the second direction, a minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion on the substrate is smaller than a minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the second conductive portion on the substrate.

4. The display substrate according to claim 1 , wherein the sub-pixel further comprises: a gate line pattern and a light emitting control signal line pattern both extending along a second direction, the second direction intersecting the first direction,
the sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switching transistors include a fourth transistor and a fifth transistor;
a gate electrode of the fourth transistor is coupled to the gate line pattern, a first electrode of the fourth transistor is coupled to the data line pattern, and a second electrode of the fourth transistor is coupled to a second electrode of the fifth transistor, a gate electrode of the fifth transistor is coupled to the light emitting control signal line pattern, and a first electrode of the fifth transistor is coupled to the power signal line pattern;
a gate electrode of the first transistor is coupled to the gate line pattern, a second electrode of the first transistor is coupled to the gate electrode of the driving transistor, the first electrode of the first transistor, a first electrode of the sixth transistor and the second electrode of the driving transistor are formed as an integral structure, and the integral structure includes a second conductive portion extending along the first direction, a gate electrode of the sixth transistor is coupled to the light emitting control signal line pattern, and a second electrode of the sixth transistor is coupled to the light emitting element in the sub-pixel;
an orthographic projection of a channel region of the driving transistor on the substrate is located between an orthographic projection of the first conductive portion on the substrate and an orthographic projection of the second conductive portion on the substrate; the first electrode and the second electrode of the driving transistor both include a first portion extending along the second direction, and a length of the first portion of the first electrode along the second direction is different from a length of the first portion of the second electrode along the second direction.

5. The display substrate according to claim 1 , wherein the sub-pixel further comprises an initialization signal line pattern, the initialization signal line pattern includes a portion extending along a second direction, and the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;
the sub-pixel driving circuit further includes a second transistor coupled to the gate electrode of the driving transistor, and the second transistor includes:
a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, conductivity of the third conductor pattern is better than conductivity of the first semiconductor pattern and conductivity of the second semiconductor pattern;
a first gate pattern and the second gate pattern, an orthographic projection of the first gate pattern on the substrate at least partially overlaps an orthographic projection of the first semiconductor pattern on the substrate, an orthographic projection of the second gate pattern on the substrate at least partially overlaps an orthographic p

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Diao Yongfu
• Chen Chenyu

Classifications

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title