Damascene-based approaches for embedding spin hall MTJ devices into a logic processor and the resulting structures

Patent metadata

Field	Value
Publication number	US-11469268-B2
Application number	US-201616067803-A
Country	US
Kind code	B2
Filing date	Mar 18, 2016
Priority date	Mar 18, 2016
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.

First claim

What is claimed is:

1. A logic processor, comprising:
a logic region comprising a metallization layer; and
a memory array comprising a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells, wherein spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region, the lower dielectric layer over a plurality of metal lines, and MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region, wherein the lower dielectric layer is a single dielectric material layer, wherein a top surface of the spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells is co-planar with a top surface of the lower dielectric layer, wherein a bottom surface of the spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells is co-planar with a bottom surface of the lower dielectric layer, wherein the upper dielectric layer has a top surface and the memory array comprises an insulating spacer layer disposed adjacent to sidewalls of the MTJs of the 2T-1MTJ SHE electrode bit cells, the insulating spacer layer having a top surface co-planar with the top surface of the upper dielectric layer, and wherein the memory array comprises an etch stop layer below the lower dielectric layer and above the plurality of metal lines, a first conductive via in the etch stop layer and on a first one of the metal lines, a second conductive via in the etch stop layer and on a second one of the metal lines, the first conductive via and the second conductive via having a top surface co-planar with a top surface of the etch stop layer, the first conductive via having a width greater than a width of the first one of the metal lines, wherein one of the spin hall effect electrodes is coupled to the first one of the metal lines by the first conductive via, wherein the one of the spin hall effect electrodes is coupled to the second one of the metal lines by the second conductive via, and wherein the one of the spin hall effect electrodes completely overlaps the first conductive via and the second conductive via.

2. The logic processor of claim 1 , wherein the insulating spacer layer is further across a top surface of the spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells.

3. The logic processor of claim 2 , wherein the insulating spacer layer extends across a top surface of the lower dielectric layer.

4. The logic processor of claim 1 , wherein the metallization layer comprises a layer of metal lines and corresponding vias disposed in the lower and upper dielectric layers.

5. The logic processor of claim 4 , wherein the lower and upper dielectric layers meet at a seam in the metallization layer.

6. The logic processor of claim 4 , wherein the vias are disposed in both of the lower and upper dielectric layers, and the metal lines are disposed only in the upper dielectric layer.

7. The logic processor of claim 1 , wherein the memory array comprises a plurality of bit lines disposed in a dielectric layer disposed above the upper dielectric layer.

8. The logic processor of claim 1 , wherein the spin hall electrode of each of the 2T-1MTJ SHE electrode bit cells comprises a metal selected from the group consisting of β-Tantalum (β-Ta), β-Tungsten (β-W), platinum (Pt), Cu doped with Bi, iridium (Ir), tungsten (W), a Ag/Bi bilayer, BiSe, or MoS 2 .

9. The logic processor of claim 1 , wherein a transistor of each of the 2T-1MTJ SHE electrode bit cells comprises two semiconductor fins.

10. A semiconductor structure, comprising:
a first plurality and a second plurality of semiconductor devices disposed above a substrate;
a plurality of metal 1 (M 1 ) lines disposed in a first dielectric layer disposed above the first plurality of semiconductor devices, and a plurality of source lines disposed in the first dielectric layer above the second plurality of semiconductor devices;
a plurality of metal 2 (M 2 ) lines disposed in an upper layer of a second dielectric layer disposed above a lower layer of the second dielectric layer disposed above the M 1 lines, and a plurality of spin hall effect electrode (SHE electrode)/magnetic tunnel junction (MTJ) stack pairings disposed in the second dielectric layer above plurality of source lines, the SHE electrodes disposed in the lower dielectric layer of the second dielectric layer, and the MTJ stacks disposed in the upper dielectric layer of the second dielectric layer, wherein the lower dielectric layer is a single dielectric material layer, wherein a top surface of the SHE electrodes is co-planar with a top surface of the lower dielectric layer of the second dielectric layer, wherein a bottom surface of the SHE electrodes is co-planar with a bottom surface of the lower dielectric layer of the second dielectric layer, and wherein the upper dielectric layer of the second dielectric layer has a top surface co-planar with a top surface of the M 2 lines, wherein an etch stop layer is below the lower layer of the second dielectric layer and above the plurality of source lines, a first conductive via in the etch stop layer and on a first one of the source lines, a second conductive via in the etch stop layer and on a second one of the source lines, the first conductive via and the second conductive via having a top surface co-planar with a top surface of the etch stop layer, the first conductive via having a width greater than a width of the first one of the source lines, wherein one of the SHE electrodes is coupled to the first one of the source lines by the first conductive via, wherein the one of the SHE electrodes is coupled to the second one of the source lines by the second conductive via, and wherein the one of the SHE electrodes completely overlaps the first conductive via and the second conductive via;
an insulating spacer layer disposed adjacent to sidewalls of the MTJ stacks, the insulating spacer layer having a top surface co-planar with the top surface of the upper dielectric layer of the second dielectric layer; and
a plurality of metal 3 (M 3 ) lines disposed in a third dielectric layer disposed above the plurality of M 2 lines, and a plurality of bitlines disposed in the third dielectric layer above the plurality of SHE electrode/MTJ stack pairings.

11. The semiconductor structure of claim 10 , further comprising:
a second etch stop layer disposed between the second and third dielectric layers.

12. The semiconductor structure of claim 10 , wherein each of the plurality of SHE electrode/MTJ stack pairings is included in a 2T-1MTJ SHE electrode bit cell.

13. The semiconductor structure of claim 10 , wherein the SHE electrode of each of the plurality of SHE electrode/MTJ stack pairings comprises a metal selected from the group consisting of β-Tantalum (β-Ta), β-Tungsten (β-W), platinum (Pt), Cu doped with Bi, iridium (Ir), tungsten (W), a Ag/Bi bilayer, BiSe, or MoS2.

14. The semiconductor structure of claim 10 , wherein each of the second plurality of semiconductor devices comprises two semiconductor fins.

15. The semiconductor structure of claim 10 , wherein each of the plurality of SHE electrode/MTJ stack pairings comprises an MTJ stack disposed on a corresponding SHE electrode.

16. A method of fabricating logic regions together with 2T-1MTJ SHE electrode STT-MRAM bit cell arrays on a common substrate, the method comprising:
forming a plurality of transistor structures above the common substrate;
forming contact metalliza

Assignees

• Intel Corp

Inventors

• Lee Kevin J
• Wang Yih

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H01F41/34

  in patterns, e.g. by lithography · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title