Array substrate, display apparatus, and method of fabricating array substrate

Patent metadata

Field	Value
Publication number	US-11469261-B2
Application number	US-201916769725-A
Country	US
Kind code	B2
Filing date	Aug 20, 2019
Priority date	Aug 20, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

An array substrate is provided. The array substrate includes a display area having a first array of subpixels; and a partially transparent area having a second array of subpixels. The partially transparent area includes a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region. The second array of subpixels is limited in the plurality of light emitting regions. The array substrate further includes a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region. A respective one of the plurality of photosensors includes a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer.

First claim

What is claimed is:

1. An array substrate, comprising:
a display area comprising a first array of subpixels; and
a partially transparent area comprising a second array of subpixels;
wherein the partially transparent area comprises a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region;
the second array of subpixels is limited in the plurality of light emitting regions; and
the array substrate further comprises a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region;
wherein a respective one of the plurality of photosensors comprises a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer;
a respective one of the plurality of first thin film transistors comprises a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer; and
the first array of subpixels has a number density of subpixels higher than a number density of subpixels of the second array of subpixels.

2. The array substrate of claim 1 , wherein a respective one of the plurality of light emitting regions comprises multiple subpixels of the second array of subpixels;
the respective one of the plurality of light emitting regions is substantially surrounded by one or more photosensors of the plurality of photosensors; and
multiple photosensors of the plurality of photosensors in the substantially transparent non-light emitting region are electrically connected in parallel to a same one of the plurality of first thin film transistors.

3. The array substrate of claim 2 , wherein, in the display area and the plurality of light emitting regions of the partially transparent area, the array substrate comprises a plurality of second thin film transistors for driving light emission in the display area and the plurality of light emitting regions;
wherein the array substrate further comprises a passivation layer on a side of the plurality of photosensors, the plurality of first thin film transistors, and the plurality of second thin film transistors away from a base substrate; and
one or more layers on a side of the passivation layer away from the base substrate, and limited in the display area and in the plurality of light emitting regions of the partially transparent area;
wherein the one or more layers are absent in the substantially transparent non-light emitting region.

4. The array substrate of claim 1 , wherein the second polarity semiconductor layer is electrically connected to a bias electrode; and
the bias electrode, the first source electrode, and the first drain electrode are in a same layer and comprise a same material.

5. The array substrate of claim 1 , wherein, in the display area and the plurality of light emitting regions of the partially transparent area, the array substrate comprises a plurality of second thin film transistors for driving light emission in the display area and the plurality of light emitting regions;
a respective one of the plurality of second thin film transistors comprises a second gate electrode, a second active layer, and a second source electrode and a second drain electrode respectively connected to the second active layer;
the second active layer, the intrinsic semiconductor layer, and the first active layer are in the same layer and comprise the same polysilicon material.

6. The array substrate of claim 5 , wherein the second polarity semiconductor layer is electrically connected to a bias electrode; and
the bias electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are in a same layer and comprise a same material.

7. The array substrate of claim 1 , wherein multiple photosensors of the plurality of photosensors in the substantially transparent non-light emitting region are electrically connected in parallel to a same bias electrode.

8. The array substrate of claim 1 , further comprising a light shielding layer substantially surrounding a respective one of the plurality of light emitting regions, and configured to shield at least a portion of light emitted out of the respective one of the plurality of light emitting regions from being received by an adjacent photosensor in the substantially transparent non-light emitting region.

9. The array substrate of claim 1 , further comprising a light shielding layer substantially surrounding a respective one of the plurality of photosensors, and configured to shield the respective one of the plurality of photosensors from light emitted out of an adjacent subpixel in the plurality of light emitting regions.

10. The array substrate of claim 1 , further comprising a buffer layer between the first active layer and a base substrate;
wherein the first active layer and the first polarity semiconductor layer are in direct contact with the buffer layer.

11. The array substrate of claim 1 , wherein the first polarity semiconductor layer comprises amorphous silicon doped with a P-type dopant; and
the second polarity semiconductor layer comprises indium tin oxide.

12. The array substrate of claim 1 , wherein the first array of subpixels comprises first subpixels of a first color, first subpixels of a second color, and first subpixels of a third color;
the second array of subpixels comprises second subpixels of the first color, second subpixels of the second color, and second subpixels of the third color;
a number density of the first subpixels of the first color is substantially the same as a number density of the second subpixels of the first color;
a number density of the first subpixels of the second color is substantially the same as a number density of the second subpixels of the second color; and
a number density of the first subpixels of the third color is approximately twice of a number density of the second subpixels of the third color.

13. A display apparatus, comprising the array substrate of claim 1 , and one or more integrated circuits connected to the array substrate.

14. An array substrate, comprising:
a display area comprising a first array of subpixels; and
a partially transparent area comprising a second array of subpixels;
wherein the partially transparent area comprises a plurality of light emitting regions spaced apart from each other by a substantially transparent non-light emitting region;
the second array of subpixels is limited in the plurality of light emitting regions; and
the array substrate further comprises a plurality of photosensors and a plurality of first thin film transistors in the substantially transparent non-light emitting region;
wherein a respective one of the plurality of photosensors comprises a first polarity semiconductor layer, a second polarity semiconductor layer, and an intrinsic semiconductor layer connecting the first polarity semiconductor layer and the second polarity semiconductor layer; and
a respective one of the plurality of first thin film transistors comprises a first gate electrode, a first active layer, and a first source electrode and a first drain electrode respectively connected to the first active layer;
wherein the intrinsic semiconductor layer and the first active layer are in a same layer and comprise a same polysilicon material;
the first polarity semiconductor layer is electrically connected to the first source electrode; and
the second polarity semicon

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Ban Shengguang
• Cao Zhanfeng
• Wang Ke
• Liu Qingzhao
• Dong Shuilang

Classifications

• G02F1/13318 Primary

  Circuits comprising a photodetector · CPC title

• G06V40/13

  Sensors therefor · CPC title

• G02F1/13312

  Circuits comprising photodetectors for purposes other than feedback · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/13685

  Top gates · CPC title