Manufacturing method of array substrate using dry etching processing and wet etching processing, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11469253-B2
Application number	US-201716074976-A
Country	US
Kind code	B2
Filing date	Nov 14, 2017
Priority date	May 27, 2017
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A manufacturing method of an array substrate, an array substrate and a display device are disclosed. The manufacturing method of the array substrate includes: providing a base substrate (200); forming a semiconductor layer on the base substrate; depositing an etch stop layer material on the semiconductor layer; subjecting the etch stop layer material to a wet etching process to form an etch stop layer; subjecting the semiconductor layer to a dry etching process to form an active layer, wherein the active layer includes a first region and a second region surrounding the first region, an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate.

First claim

What is claimed is:

1. A manufacturing method of an array substrate, comprising:
providing a base substrate;
forming a semiconductor layer on the base substrate;
depositing an etch stop layer material on the semiconductor layer;
forming an etch stop layer by subjecting the etch stop layer material to a wet etching process; and
after the forming the etch stop layer, forming an active layer by subjecting the semiconductor layer to a dry etching process,
wherein the active layer comprises a first region and a second region surrounding the first region, and an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate,
wherein the forming the etch stop layer comprises:
forming a mask pattern on the etch stop layer material; and
etching etch stop layer material uncovered by the mask pattern and located on the second region of the active layer with the mask pattern as a mask so as to form the etch stop layer, wherein the etch stop layer is located on the first region of the active layer,

wherein the forming the active layer comprises:
etching the semiconductor layer with the mask pattern as the mask.

2. The manufacturing method of the array substrate according to claim 1 , wherein, along a direction parallel with the base substrate, a minimum distance between an edge of the etch stop layer and an edge of the active layer is in a range of 0.5-1.5 μm.

3. The manufacturing method of the array substrate according to claim 1 , further comprising:
forming a source electrode and a drain electrode on the etch stop layer,
wherein, each of the source electrode and the drain electrode is in contact with a portion of the second region of the active layer.

4. The manufacturing method of the array substrate according to claim 1 , wherein an etching liquid used in the wet etching process has an etch selectivity ratio of the etch stop layer material to the semiconductor layer which is greater than 1000:1.

5. The manufacturing method of the array substrate according to claim 1 , wherein a material of the etch stop layer comprises at least one selected from the group consisting of an oxide of silicon, a nitride of silicon, and a combination thereof.

6. The manufacturing method of the array substrate according to claim 1 , wherein the semiconductor layer is a poly-silicon layer, and the forming the semiconductor layer on the base substrate comprises:
depositing an amorphous silicon layer on the base substrate, and crystallizing, by a laser annealing process, the amorphous silicon layer to form the poly-silicon layer.

7. A manufacturing method of an array substrate, comprising:
providing a base substrate;
forming a semiconductor layer on the base substrate;
depositing an etch stop layer material on the semiconductor layer;
forming an etch stop layer by subjecting the etch stop layer material to a wet etching process; and
after the forming the etch stop layer, forming an active layer by subjecting the semiconductor layer to a dry etching process,
wherein the active layer comprises a first region and a second region surrounding the first region, and an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate,
the forming the etch stop layer comprises:
forming a mask pattern on the etch stop layer material; and
etching etch stop layer material uncovered by the mask pattern and located on the second region of the active layer with the mask pattern as a mask so as to form the etch stop layer, wherein the etch stop layer is located on the first region of the active layer,

the forming the active layer comprises: etching the semiconductor layer with the mask pattern as a mask,
wherein, along a direction parallel with the base substrate, a minimum distance between an edge of the etch stop layer and an edge of the active layer is in a range of 0.5-1.5 μm,
wherein an etching liquid used in the wet etching process has an etch selectivity ratio of the etch stop layer material to the semiconductor layer which is greater than 1000:1.

8. The manufacturing method of the array substrate according to claim 7 , further comprising:
forming a source electrode and a drain electrode on the etch stop layer,
wherein each of the source electrode and the drain electrode is in contact with a portion of the second region of the active layer.

9. The manufacturing method of the array substrate according to claim 7 , wherein a material of the etch stop layer comprises at least one selected from the group consisting of an oxide of silicon, a nitride of silicon, and a combination thereof.

10. The manufacturing method of the array substrate according to claim 7 , wherein the semiconductor layer is a poly-silicon layer, and the forming the semiconductor layer on the base substrate comprises:
depositing an amorphous silicon layer on the base substrate, and crystallizing, by a laser annealing process, the amorphous silicon layer to form the poly-silicon layer.

Assignees

• Beijing Boe Technology Dev Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Cao Binbin
• Qian Haijiao
• Yang Chengshao
• Huang Yinhu

Classifications

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H01L27/1222 Primary

  Electricity · mapped topic

• H01L27/127

  Electricity · mapped topic

• H01L27/1288

  Electricity · mapped topic

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title