System and method for detecting memory cell disturbance by monitoring canary cells

Patent metadata

Field	Value
Publication number	US-11468942-B2
Application number	US-202117189897-A
Country	US
Kind code	B2
Filing date	Mar 2, 2021
Priority date	Mar 2, 2021
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

One embodiment provides a memory module. The memory module includes a plurality of rows of memory cells, with a respective row comprising one or more canary memory cells that are more susceptible to disturbance than non-canary memory cells, and a disturbance-detection circuit coupled to at least one canary memory cell of a corresponding row and configured to output a control signal in response to the disturbance to the canary memory cell exceeding a predetermined threshold.

First claim

What is claimed is:

1. A memory module, comprising:
a plurality of rows of memory cells, wherein a respective row comprises one or more canary memory cells that are more susceptible to disturbance than non-canary memory cells; and
a disturbance-detection circuit coupled to at least one canary memory cell of a corresponding row and configured to output a control signal in response to detecting disturbance to the canary memory cell exceeding a predetermined threshold;
wherein the disturbance-detection circuit comprises at least a first transistor coupled to a capacitor within the canary memory cell, wherein the first transistor is configured to be turned on when the disturbance to the canary memory cell exceeds the predetermined threshold.

2. The memory module of claim 1 , wherein the capacitor is charged to a predetermined level without the disturbance, wherein the disturbance causes the capacitor to discharge, and wherein the first transistor is a p-type transistor such that the p-type transistor is turned on when the capacitor is discharged to a predetermined level.

3. The memory module of claim 2 , wherein a group of canary memory cells are respectively coupled to a group of p-type transistors, and wherein the group of p-type transistors are coupled to each other in parallel such that a status change of any one p-type transistor results in the control signal being outputted by the disturbance-detection circuit.

4. The memory module of claim 1 , wherein the capacitor is discharged without the disturbance, wherein the disturbance causes the capacitor to charge, and wherein the first transistor is an n-type transistor such that the n-type transistor is turned on when the capacitor is charged to a predetermined level.

5. The memory module of claim 4 , wherein a group of canary memory cells are respectively coupled to a group of n-type transistors, and wherein the group of n-type transistors are coupled to each other in parallel such that a status change of any one n-type transistor results in the control signal being outputted by the disturbance-detection circuit.

6. The memory module of claim 1 , wherein the disturbance-detection circuit comprises a second transistor coupled to the first transistor, wherein an on-off status of the second transistor is determined by an on-off status of the first transistor, and wherein the disturbance-detection circuit is configured to output the control signal in response to a change of the on-off status of the second transistor.

7. The memory module of claim 1 , further comprising a control logic, wherein the control logic is configured to:
in response to detecting the control signal, schedule a refresh operation on the corresponding row; or
in response to detecting the control signal, send a notification signal to an external memory controller coupled to the memory module, thereby facilitating the external memory controller to schedule a refresh operation on the corresponding row.

8. The memory module of claim 7 , wherein the memory module implements refresh management (RFM), and wherein scheduling the refresh operation comprises adding an address associated with the corresponding row to a to-be-executed RFM command.

9. The memory module of claim 7 , wherein the control logic is further configured to:
in response to detecting a collision between the scheduled refresh operation and a memory-access command issued by a memory controller, sending an error message to the memory controller to request the memory controller to resend the memory-access command.

10. A method for detecting disturbance to a memory module, comprising:
including one or more canary memory cells in each row of the memory module, wherein the canary memory cells are more susceptible to the disturbance than non-canary memory cells; and
outputting, by a disturbance-detection circuit coupled to at least one canary memory cell of a corresponding row, a control signal, in response to detecting the disturbance to the canary memory cell exceeding a predetermined threshold;
wherein the disturbance-detection circuit comprises at least a first transistor coupled to a capacitor within the canary memory cell, wherein the first transistor is configured to be turned on when the disturbance to the canary memory cell exceeds the predetermined threshold.

11. The method of claim 10 , wherein the capacitor is charged to a predetermined level without disturbance, wherein the disturbance causes the capacitor to discharge, and wherein the first transistor is a p-type transistor such that the p-type transistor is turned on when the capacitor is discharged to a predetermined level.

12. The method of claim 11 , further comprising:
respectively coupling a group of p-type transistors to a group of canary memory cells; and
coupling the group of p-type transistors to each other in parallel such that a status change of any one p-type transistor results in the control signal being outputted by the disturbance-detection circuit.

13. The method of claim 10 , wherein the capacitor is discharged without disturbance, wherein the disturbance causes the capacitor to charge, and wherein the first transistor is an n-type transistor such that the n-type transistor is turned on when the capacitor is charged to a predetermined level.

14. The method of claim 13 , further comprising:
respectively coupling a group of n-type transistors to a group of canary memory cells; and
coupling the group of n-type transistors to each other in parallel such that a status change of any one n-type transistor results in the control signal being outputted by the disturbance-detection circuit.

15. The method of claim 10 , wherein the disturbance-detection circuit comprises a second transistor coupled to the first transistor, wherein an on-off status of the second transistor is determined by an on-off status of the first transistor, and wherein outputting the control signal comprises:
in response to detecting a change of the on-off status of the second transistor, outputting the control signal.

16. The method of claim 10 , further comprising:
in response to detecting, by a control logic of the memory module, the control signal, scheduling a refresh operation on the corresponding row; or
in response to detecting, by the control logic of the memory module, the control signal, sending a notification signal to an external memory controller coupled to the memory module, thereby facilitating the external memory controller to schedule a refresh operation on the corresponding row.

17. The method of claim 16 , wherein the memory module implements refresh management (RFM), and wherein scheduling the refresh operation comprises adding an address associated with the corresponding row to a to-be executed RFM command.

18. The method of claim 16 , further comprising:
in response to detecting a collision between the scheduled refresh operation and a memory-access command issued by a memory controller, sending an error message to the memory controller to request the memory controller to resend the memory-access command.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Benedict Melvin K
• Pope Eric L

Classifications

• G11C2029/5004

  Voltage · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/40603

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title