Array substrate and method for manufacturing same, display panel, and display device

Patent metadata

Field	Value
Publication number	US-11468832-B2
Application number	US-201917256039-A
Country	US
Kind code	B2
Filing date	Nov 8, 2019
Priority date	Nov 8, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

An array substrate includes a base substrate, a pixel circuit, a flexible substrate, a lead structure, a control circuit and a planarization layer. The flexible substrate includes a first substrate portion and a second substrate portion, and the lead structure includes a first lead portion and a second lead portion. The pixel circuit, the first lead portion and the first substrate portion are all arranged on a first side of the base substrate, the control circuit, the second lead portion and the second substrate portion are all arranged on a second side of the base substrate, and the second side is opposite to the first side.

First claim

What is claimed is:

1. An array substrate, comprising: a base substrate, a pixel circuit, a lead structure, a control circuit, a flexible substrate and a planarization layer; wherein
the flexible substrate comprises a first substrate portion, a curved substrate portion and a second substrate portion which are sequentially connected, the pixel circuit and a first substrate portion are both arranged on a first side of the base substrate, the curved substrate portion is curved from the first side of the base substrate to a second side, and the second substrate portion is arranged on the second side of the base substrate the second side is opposite to the first side;
the lead structure comprises a first lead portion, a curved lead portion and a second lead portion which are sequentially connected, the first lead portion is arranged on a side, distal from the base substrate, of the first substrate portion and is electrically connected to the pixel circuit, the curved lead portion is arranged on a side, distal from the base substrate, of the curved substrate portion, and the second lead portion is arranged on one side, distal from the base substrate, of the second substrate portion and is electrically connected to the control circuit arranged on the second side of the base substrate; and
the planarization layer is arranged on a side, distal from the base substrate, of the pixel circuit and covers the pixel circuit, the first lead portion and the curved lead portion.

2. The array substrate according to claim 1 , wherein the base substrate is a rigid substrate.

3. The array substrate according to claim 1 , wherein the array substrate further comprises an auxiliary film layer and the lead structure.

4. The array substrate according to claim 1 , wherein the array substrate further comprises a target cushion layer;
the target cushion layer comprises a first cushion layer portion and a second cushion layer portion, and a viscosity of the second cushion layer portion is larger than that of the first cushion layer portion; and
the pixel circuit is arranged on a side, distal from the base substrate of the first cushion layer portion, and the first substrate portion is arranged on a side, distal from the base substrate, of the second cushion layer portion.

5. The array substrate according to claim 1 , wherein the surface, distal from the base substrate, of the first substrate portion is provided with a first protrusion;
an orthographic projection of the first protrusion on the base substrate has an overlapping region with an orthographic projection of a sealant on the base substrate, and the sealant is used for sealing the array substrate and a cover plate arranged on the side, distal from the base substrate, of the pixel circuit.

6. The array substrate according to claim 5 , wherein a height of the first protrusion is equal to a thickness of the sealant in a direction perpendicular to the base substrate.

7. The array substrate according to claim 5 , wherein the array substrate further comprises an auxiliary substrate;
the auxiliary substrate and the flexible substrate are arranged at one layer, form an annular shape in an enclosing manner and surround a display region of the base substrate; and
a surface, distal from the base substrate, of auxiliary substrate is provided with a second protrusion, and an orthographic projection of the second protrusion on the base substrate has an overlapping region with an orthographic projection of the sealant on the base substrate.

8. The array substrate according to claim 7 , wherein a ratio of a sum of areas of orthographic projections of a top surface of the first protrusion and a top surface of the second protrusion on the base substrate in the array substrate to an area of an orthographic projection of the sealant on the base substrate is larger than two thirds.

9. The array substrate according to claim 1 , wherein the array substrate further comprises an adhesive; and
the adhesive comprises a first adhesive portion, a second adhesive portion and a third adhesive portion which are sequentially connected, wherein the first adhesive portion is arranged between the base substrate and the first substrate portion, the second adhesive portion is arranged between the base substrate and the curved substrate portion, and the third adhesive portion is arranged between the base substrate and the second substrate portion.

10. The array substrate according to claim 9 , wherein the array substrate further comprises a first buffer structure, and the first buffer structure is arranged between the second adhesive portion and the curved substrate portion.

11. The array substrate according to claim 1 , wherein the array substrate further comprises a second buffer structure; and
the second buffer structure is arranged between the base substrate and the control circuit, and an orthographic projection of the second buffer structure on the base substrate has an overlapping region with an orthographic projection of the control circuit on the base substrate.

12. The array substrate according to claim 1 , wherein the curved lead portion is arranged in a fan-out region in the lead structure, and the second lead portion is provided with a pin which is electrically connected to the control circuit.

13. The array substrate according to claim 4 , wherein one end, proximal to the first cushion layer portion, of the second cushion layer portion is flush with one end, proximal to the first cushion layer portion, of the first substrate portion, and one end, distal from the first cushion layer portion, of the second cushion layer portion is flush with one end, distal from the first cushion layer portion, of the base substrate.

14. The array substrate according to claim 1 , wherein the array substrate further comprises a bonding substrate arranged between the base substrate and the second substrate portion.

15. The array substrate according to claim 14 , wherein the base substrate and the bonding substrate are made of a same material, and a thickness of the base substrate is equal to that of the bonding substrate.

16. The array substrate according to claim 15 , wherein the thickness of the base substrate is smaller than or equal to that of a cover plate in a display panel, the base substrate is disposed on the display panel, and the cover plate is arranged on the side, distal from the base substrate, of the pixel circuit.

17. A method for manufacturing an array substrate, the method being used for manufacturing the array substrate according to claim 1 , and comprising:
forming a base substrate, a pixel circuit, a lead structure, a flexible substrate, a control circuit and a planarization layer, wherein the pixel circuit, the flexible substrate, the control circuit and the planarization layer are all arranged on a first side of the base substrate; an orthographic projection of the flexible substrate on a reference plane parallel to the base substrate overlaps an orthographic projection portion of the base substrate on the reference plane; the lead structure covers a side, distal from the base substrate, of the flexible substrate and is electrically connected to both the pixel circuit and the control circuit; and the planarization layer is arranged on a side, distal from the base substrate, of the pixel circuit and covers the pixel circuit and a portion, distal from the control circuit, in the lead structure; and
curving the flexible substrate and the lead structure to enable the control circuit to move from the first side of the base substrate to a second side of the base substrate, where

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Zhu Xiaoyan
• Huang Hua
• Yuan Guangcai
• Dong Xue

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• Y02P70/50

  Manufacturing or production processes characterised by the final manufactured product · CPC title

• G09F9/30

  in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09F9/33 Primary

  being semiconductor devices, e.g. diodes · CPC title