Control circuit configuration for shift register unit, gate driving circuit and display device, and method for driving the shift register unit

Patent metadata

Field	Value
Publication number	US-11468820-B2
Application number	US-201916621217-A
Country	US
Kind code	B2
Filing date	Jul 12, 2019
Priority date	Sep 11, 2018
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a display device. The shift register unit includes: an input sub-circuit configured to receive an input control signal and an input signal, and transmit the input signal to a first pull-down node of the shift register unit under control of the input control signal; a first control sub-circuit configured to receive a first clock signal and electrically couple the first pull-down node to a second pull-down node of the shift register unit under control of the first clock signal; and an output sub-circuit configured to receive a first constant voltage signal and transmit the first constant voltage signal to an output terminal of the shift register unit under control of a voltage at the second pull-down node.

First claim

I claim:

1. A shift register unit, comprising:
an input sub-circuit electrically coupled to a first pull-down node of the shift register unit, and configured to receive an input control signal and an input signal, and transmit the input signal to the first pull-down node under control of the input control signal;
a first control sub-circuit electrically coupled to the first pull-down node and a second pull-down node of the shift register unit, and configured to receive a first clock signal and electrically couple the first pull-down node to the second pull-down node of the shift register unit under control of the first clock signal;
an output sub-circuit electrically coupled to the second pull-down node, the first pull-down node, and an output terminal of the shift register unit, and configured to receive a first constant voltage signal and transmit the first constant voltage signal to the output terminal to be output as an output signal based on a voltage at the first pull-down node under control of a voltage at the second pull-down node; and
a second control sub-circuit electrically coupled to the second pull-down node and a pull-up node of the shift register unit, and configured to receive the first constant voltage signal, a second constant voltage signal, and a second clock signal and transmit the first constant voltage signal or the second constant voltage signal to the pull-up node under control of the second clock signal and the voltage at the second pull-down node,
wherein the second control sub-circuit comprises a fifth transistor and a sixth transistor, wherein:
the fifth transistor has a gate electrically coupled to receive the second clock signal, a first electrode electrically coupled to receive the first constant voltage signal, and a second electrode electrically coupled to the pull-up node; and
the sixth transistor has a gate directly connected to the second pull-down node, a first electrode electrically coupled to receive the second constant voltage signal, and a second electrode electrically coupled to the pull-up node.

2. The shift register unit according to claim 1 , wherein the output sub-circuit is further electrically coupled to the pull-up node, and is further configured to receive the second constant voltage signal and transmit the second constant voltage signal to the output terminal to be output as the output signal under control of a voltage at the pull-up node.

3. The shift register unit according to claim 2 , wherein the output sub-circuit comprises a third transistor, a fourth transistor, and a first capacitor, wherein
the third transistor has a gate electrically coupled to the second pull-down node, a first electrode electrically coupled to receive the first constant voltage signal, and a second electrode electrically coupled to the output terminal;
the fourth transistor has a gate electrically coupled to the pull-up node, a first electrode electrically coupled to receive the second constant voltage signal, and a second electrode electrically coupled to the output terminal; and
the first capacitor has a first terminal electrically coupled to the first pull-down node, and a second terminal electrically coupled to the output terminal.

4. The shift register unit according to claim 3 , wherein the output sub-circuit further comprises a second capacitor having a first terminal electrically coupled to the pull-up node, and a second terminal electrically coupled to receive the second constant voltage signal.

5. The shift register unit according to claim 1 , further comprising:
a reset sub-circuit electrically coupled to the second pull-down node, and configured to receive a reset control signal and a second constant voltage signal, and reset the second pull-down node using the second constant voltage signal under control of the reset control signal.

6. The shift register unit according to claim 5 , wherein the reset sub-circuit comprises a seventh transistor having a gate electrically coupled to receive the reset control signal, a first electrode electrically coupled to receive the second constant voltage signal, and a second electrode electrically coupled to the second pull-down node.

7. The shift register unit according to claim 6 , wherein the reset control signal is a second clock signal.

8. The shift register unit according to claim 6 , wherein the reset sub-circuit further comprises an eighth transistor having a gate electrically coupled to receive the reset control signal, a first electrode electrically coupled to receive the second constant voltage signal, and a second electrode electrically coupled to the first pull-down node.

9. The shift register unit according to claim 8 , wherein the reset control signal is an output signal from another shift register unit.

10. The shift register unit according to claim 1 , wherein the input sub-circuit comprises a first transistor having a gate electrically coupled to receive the input control signal, a first electrode electrically coupled to receive the input signal, and a second electrode electrically coupled to the first pull-down node.

11. The shift register unit according to claim 10 , wherein the input control signal is a second clock signal or the input signal.

12. The shift register unit according to claim 1 , wherein the first control sub-circuit comprises a second transistor having a gate electrically coupled to receive the first clock signal, a first electrode electrically coupled to the first pull-down node, and a second electrode electrically coupled to the second pull-down node.

13. A gate driving circuit comprising N stages of cascaded shift register units according to claim 1 , wherein an n th stage of shift register unit receives an output signal from an (n-1) th stage of shift register unit as an input signal of the n th stage of shift register unit, where n and N are integers, N≥2, and 2≤n≤N.

14. The gate driving circuit according to claim 13 , wherein each stage of shift register unit receives a second clock signal as a reset control signal; or
the N th stage of shift register unit receives an output signal from an (n+1) th stage of shift register unit as a reset control signal of the n th stage of shift register unit.

15. A display device comprising the gate driving circuit according to claim 13 .

16. A method for driving the shift register unit according to claim 1 , comprising:
transmitting, in an input period, by the input sub-circuit, an input signal at a first level to the first pull-down node under control of an input control signal; and
electrically coupling, in an output period, by the first control sub-circuit, the first pull-down node to the second pull-down node under control of a first clock signal, and causing, by a voltage at the second pull-down node, the output sub-circuit to transmit a first constant voltage signal to the output terminal of the shift register unit to be output as an output signal.

17. The method according to claim 16 , wherein the shift register unit further comprises a reset sub-circuit and a second control sub-circuit, the method further comprising:
resetting, in a reset period, by the reset sub-circuit, the second pull-down node using a second constant voltage signal under control of a reset control signal, causing, by the voltage at the second pull-down node, the second control sub-circuit to transmit the first constant voltage signal to the pull-up node of the shift register unit under control of a second clock signal, and causing, by a voltage at the pull-up node, the output sub-circuit to transmit the second constant voltage signal

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Weng Zuwei

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title