Unified register file for supporting speculative architectural states

Patent metadata

Field	Value
Publication number	US-11467839-B2
Application number	US-201615353549-A
Country	US
Kind code	B2
Filing date	Nov 16, 2016
Priority date	Jan 27, 2011
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A method for supporting architecture speculation in an out of order processor is disclosed. The method comprises fetching two threads into the processor, wherein a first thread executes in a speculative state and a second thread executes in a non-speculative state. The method also comprises enabling a speculative scope for an execution of the first thread and a non-speculative scope for an execution of the second thread in an architecture of the processor, wherein the speculative scope and the non-speculative scope can both be fetched into the architecture and be present concurrently.

First claim

What is claimed is:

1. A method for supporting architecture speculation in an out of order processor, the method comprising:
fetching two threads into the processor, wherein a first thread executes in a speculative state and a second thread executes in a non-speculative state; and
enabling a speculative scope for an execution of the first thread and a non-speculative scope for an execution of the second thread in an architecture of the processor, wherein the speculative scope and the non-speculative scope can both be fetched into the architecture and be present concurrently,
wherein in a non-speculative mode, register reads are from committed registers, register writes are to committed registers, and memory writes are written to memory,
wherein in a speculative mode, register writes are written to speculative scratch shadow registers, register reads are from a latest write, and memory writes to a retirement memory buffer, and
wherein code in the speculative mode is rolled back when an exception occurs where a state of the speculative scratch shadow registers is rolled back to a state of the committed registers, where the state of the speculative scratch shadow registers includes register values set by the first thread and the state of the committed registers includes register values set by the second thread, wherein the rollback is executed based on changing a value of an entry selector field for a register pair in a unified register file from a first value to a second value, wherein the first value indicates that a first register of the register pair is speculative and a second register of the register pair is committed, wherein the second value indicates that the first register is not valid and the second register is committed.

2. The method of claim 1 , wherein the speculative scope sets its respective mode differently from the non-speculative scope.

3. The method of claim 2 , wherein both a speculative scope and a non-speculative scope execute simultaneously.

4. The method of claim 1 , wherein the first register is read upon a read request when the value of the entry selector field for the register pair is the first value, wherein the second register is read upon a read request when the value of the entry selector field for the register pair is the second value.

5. The method of claim 4 , further comprising:
changing the value of the entry selector field to change an identity of registers in the unified register file where a speculative scratch shadow register becomes a committed register upon execution of a commit operation.

6. A method for supporting architecture speculation in an out of order processor, the method comprising:
fetching two threads into the processor, wherein a first thread executes in a speculative state and a second thread executes in a non-speculative state; and
enabling a speculative scope for an execution of the first thread and a non-speculative scope for an execution of the second thread in an architecture of the processor,
wherein in a non-speculative mode, register reads are from committed registers, register writes are to committed registers, and memory writes are written to memory,
wherein in a speculative mode, register writes are written to speculative scratch shadow registers, register reads are from a latest write, and memory writes to a retirement memory buffer, and
wherein code in the speculative mode is rolled back when an exception occurs where a state of the speculative scratch shadow registers is rolled back to a state of the committed registers, where the state of the speculative scratch shadow registers includes register values set by the first thread and the state of the committed registers includes register values set by the second thread, wherein the rollback is executed based on changing a value of an entry selector field for a register pair in a unified register file from a first value to a second value, wherein the first value indicates that a first register of the register pair is speculative and a second register of the register pair is committed, wherein the second value indicates that the first register is not valid and the second register is committed.

7. The method of claim 6 , further comprising:
fetching the speculative scope and the non-speculative scope to enable both scopes to be present in the architecture concurrently.

8. The method of claim 6 , wherein the speculative scope sets its respective mode differently from the non-speculative scope.

9. A microprocessor coupled to a memory, wherein the memory has computer readable instructions which when executed by the microprocessor cause the microprocessor to implement a method for supporting architecture speculation in an out of order processor, the method comprising:
fetching two threads into the processor, wherein a first thread executes in a speculative state and a second thread executes in a non-speculative state; and
enabling a speculative scope for an execution of the first thread and a non-speculative scope for an execution of the second thread in an architecture of the processor,
wherein in a non-speculative mode, register reads are from committed registers, register writes are to committed registers, and memory writes are written to memory,
wherein in a speculative mode, register writes are written to speculative scratch shadow registers, register reads are from a latest write, and memory writes to a retirement memory buffer, and
wherein code in the speculative mode is rolled back when an exception occurs where a state of the speculative scratch shadow registers is rolled back to a state of the committed registers, where the state of the speculative scratch shadow registers includes register values set by the first thread and the state of the committed registers includes register values set by the second thread, wherein the rollback is executed based on changing a value of an entry selector field for a register pair in a unified register file from a first value to a second value, wherein the first value indicates that a first register of the register pair is speculative and a second register of the register pair is committed, wherein the second value indicates that the first register is not valid and the second register is committed.

10. The microprocessor of claim 9 , wherein the speculative scope and the non-speculative scope can both be fetched into the architecture and be present concurrently.

11. The microprocessor of claim 9 , wherein the speculative scope sets its respective mode differently from the non-speculative scope.

12. The microprocessor of claim 9 , wherein both a speculative scope and a non-speculative scope execute simultaneously.

13. The microprocessor of claim 12 , wherein one scope is fetched into the architecture after a current scope thereby allowing dependencies between scopes to be honored.

14. The microprocessor of claim 9 , wherein the first register is read upon a read request when the value of the entry selector field for the register pair is the first value, wherein the second register is read upon a read request when the value of the entry selector field for the register pair is the second value.

15. The microprocessor of claim 14 , further configured to change the value of the entry selector field to change an identity of registers in the unified register file where a speculative scratch shadow register becomes a committed register upon execution of a commit operation.

Assignees

• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/30174 Primary

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title