Systems and methods for output channel architectures in implantable pulse generators

US11464981B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11464981-B2
Application numberUS-201916397875-A
CountryUS
Kind codeB2
Filing dateApr 29, 2019
Priority dateApr 29, 2019
Publication dateOct 11, 2022
Grant dateOct 11, 2022

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Abstract

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The present disclosure provides systems and methods for an output architecture for an implantable pulse generator of a neurostimulation system. The output architecture includes a power supply, a plurality of outputs, a global source current regulator coupled to the power supply and operable to source current from the power supply to the plurality of outputs through a plurality of source current branches, a global sink current regulator operable to sink current from the plurality of outputs to ground through a plurality of sink current branches, a current source branch selector operable to select, for each of the plurality of outputs, an amount of current sourced from the plurality of source current branches, and a current sink branch selector operable to select, for each of the plurality of outputs, an amount of current sunk to the plurality of sink current branches.

First claim

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What is claimed is: 1. An output architecture for an implantable pulse generator of a neurostimulation system, the output architecture comprising: a power supply; a plurality of outputs; a global source current regulator coupled to the power supply and operable to source a first total current from the power supply to the plurality of outputs through a plurality of source current branches; a global sink current regulator operable to sink a second total current from the plurality of outputs to ground through a plurality of sink current branches; a current source branch selector operable to select, for each of the plurality of outputs, a fraction of the first total current sourced from the plurality of source current branches, wherein a sum of the fractions of current sourced to each of the plurality of outputs equals the first total current sourced, wherein the current source branch selector comprises a plurality of source selection switches, and wherein each of the plurality of outputs is couplable to each current branch of the plurality of current source branches to source the fraction of the first total current from a particular current source branch of the plurality of current source branches via activation of respective ones of the plurality of source selection switches; and a current sink branch selector operable to select, for each of the plurality of outputs, a fraction of the second total current sunk to the plurality of sink current branches, wherein a sum of the fractions of current sunk from each of the plurality of outputs equals the second total current sunk. 2. The output architecture of claim 1 , further comprising a plurality of reference voltage switches operable to selectively connect the plurality of outputs to a reference voltage, wherein the plurality of reference voltage switches are distinct from the global source current regulator. 3. The output architecture of claim 1 , further comprising a plurality of discharge switches operable to selectively connect the plurality of outputs to at least one discharge rail, and wherein the discharge rail is distinct from the global sink current regulator. 4. The output architecture of claim 1 , wherein the global source current regulator comprises a programmable resistor, and an amplifier configured as a voltage digital to analog converter. 5. The output architecture of claim 4 , further comprising a second power supply operable to power the amplifier. 6. The output architecture of claim 1 , wherein the global sink current regulator comprises a programmable resistor, and an amplifier configured as a voltage digital to analog converter. 7. The output architecture of claim 1 , wherein the output architecture is for use in a deep brain simulation system. 8. The output architecture of claim 1 , wherein the output architecture is for use in a spinal cord simulation system. 9. The output architecture of claim 1 , wherein the current source branch selector comprises a plurality of source decoders, wherein each of the plurality of source decoders is associated with a corresponding source current branch of the plurality of source current branches. 10. The output architecture of claim 1 , wherein the current sink branch selector comprises a plurality of sink decoders and a plurality of sink selection switches, wherein each of the plurality of sink decoders is associated with a corresponding sink current branch of the plurality of sink current branches. 11. A neurostimulation system comprising: a stimulation lead comprising a plurality of electrodes; and an implantable pulse generator communicatively coupled to the stimulation lead, the implantable pulse generator comprising an output architecture that comprises: a power supply; a plurality of outputs; a global source current regulator coupled to the power supply and operable to source a first total current from the power supply to the plurality of outputs through a plurality of source current branches; a global sink current regulator operable to sink a second total current from the plurality of outputs to ground through a plurality of sink current branches; a current source branch selector operable to select, for each of the plurality of outputs, a fraction of the first total current sourced from the plurality of source current branches, wherein a sum of the fractions of current sourced to each of the plurality of outputs equals the first total current sourced, wherein the current source branch selector comprises a plurality of source selection switches, and wherein each of the plurality of outputs is couplable to each current branch of the plurality of current source branches to source the fraction of the first total current from a particular current source branch of the plurality of current source branches via activation of respective ones of the plurality of source selection switches; and a current sink branch selector operable to select, for each of the plurality of outputs, a fraction of the second total current sunk to the plurality of sink current branches, wherein a sum of the fractions of current sunk from each of the plurality of outputs equals the second total current sunk. 12. The neurostimulation system of claim 11 , wherein the output architecture further comprises a plurality of reference voltage switches operable to selectively connect the plurality of outputs to a reference voltage. 13. The neurostimulation system of claim 11 , wherein the output architecture further comprises a plurality of discharge switches operable to selectively connect the plurality of outputs to at least one discharge rail. 14. The neurostimulation system of claim 11 , wherein the global source current regulator comprises a programmable resistor, and an amplifier configured as a voltage digital to analog converter. 15. The neurostimulation system of claim 14 , wherein the output architecture further comprises a second power supply operable to power the amplifier. 16. The neurostimulation system of claim 11 , wherein the global sink current regulator comprises a programmable resistor, and an amplifier configured as a voltage digital to analog converter. 17. The neurostimulation system of claim 11 , wherein the neurostimulation system is a deep brain stimulation system. 18. The neurostimulation system of claim 11 , wherein the neurostimulation system is a spinal cord stimulation system. 19. A method of assembling an output architecture for an implantable pulse generator, the method comprising: coupling a global source current regulator between a power supply and a plurality of outputs, the global source current regulator operable to source a first total current from the power supply to the plurality of outputs through a plurality of source current branches; coupling a global sink current regulator to the plurality of outputs, the global sink current regulator operable to sink a second total current from the plurality of outputs to ground through a plurality of sink current branches; coupling a current source branch selector between the global source current regulator and the plurality of outputs, the current source branch selector operable to select, for each of the plurality of outputs, a fraction of the first total current sourced from the plurality of source current branches, wherein a sum of the fractions of current sourced to each of the plurality of outputs equals the first total current sourced, wherein the current source branch selector comprises a plurality of source selection switches, and wherein each of the plurality of outputs is

Assignees

Inventors

Classifications

  • Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

  • using digital techniques · CPC title

  • Generators producing trains of pulses, i.e. finite sequences of pulses · CPC title

  • Current (A61N1/3616 takes precedence) · CPC title

  • Spinal or peripheral nerve electrodes · CPC title

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What does patent US11464981B2 cover?
The present disclosure provides systems and methods for an output architecture for an implantable pulse generator of a neurostimulation system. The output architecture includes a power supply, a plurality of outputs, a global source current regulator coupled to the power supply and operable to source current from the power supply to the plurality of outputs through a plurality of source current…
Who is the assignee on this patent?
Advanced Neuromodulation Systems Inc
What technology area does this patent fall under?
Primary CPC classification A61N1/36157. Mapped technology areas include Human Necessities.
When was this patent published?
Publication date Tue Oct 11 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).