System and method for generating time reference in duty-cycled wireless communications

Patent metadata

Field	Value
Publication number	US-11463232-B2
Application number	US-202117142214-A
Country	US
Kind code	B2
Filing date	Jan 5, 2021
Priority date	Jan 9, 2020
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

A system is provided for generating a time reference in duty-cycled wireless communications. The system includes at least one master module including a master transceiver adapted to transmit data packets. The system further includes at least one slave module including a slave transceiver adapted to receive the data packets. The slave module further includes a signal generator adapted to generate a clock signal with a period equal to the time interval of two data packets transmitted by the master module. Moreover, the slave module further includes a slave timer adapted to utilize the clock signal as a time reference in order to perform the sleep/wakeup control for the slave module.

First claim

What is claimed is:

1. A system for generating a time reference in duty-cycled wireless communications, the system comprising:
a master module comprising a master transceiver adapted to transmit data packets; and
a slave module comprising:
a slave transceiver adapted to receive the data packets;
a signal generator adapted to generate a clock signal with a period equal to a time interval of two of the data packets, wherein the signal generator is further adapted to set a flag signal in response to the data packets being detected and adapted to reset the flag signal upon completion of the data packets; and
a slave timer adapted to utilize the clock signal to control the slave module, wherein the slave timer further comprises a calibration circuit adapted to calibrate the slave timer based on the flag signal.

2. The system of claim 1 , wherein the slave timer is adapted to utilize the clock signal to wake the slave module.

3. The system of claim 1 , wherein the slave timer is adapted to utilize the clock signal to cause the slave module to sleep.

4. The system according to claim 1 , wherein the slave module is implemented on a single integrated circuit.

5. The system according to claim 1 , wherein the slave timer comprises an on-chip oscillator.

6. The system according to claim 1 , wherein the master module is further adapted to transmit the data packets with a specific duty-cycle ratio and a specific time interval between the data packets.

7. The system according to claim 1 , wherein the master module further comprises a master timer adapted to generate a time reference to control the master module.

8. The system according to claim 1 , wherein the slave module is further adapted to detect the data packets via signal detection, energy detection, preamble detection, or synchronized frame detection.

9. The system according to claim 1 , wherein the signal generator is further adapted to set a flag signal to high in response to the data packets being detected and adapted to reset the flag signal to zero upon completion of the data packets, thereby generating the clock signal such that the period is equal to the time interval.

10. The system according to claim 1 , wherein a frequency reference for the master module or the slave module is defined by a crystal oscillator, a microelectromechanical system (MEMS) based oscillator, or a bulk acoustic wave (BAW) based oscillator.

11. A method for generating a time reference in duty-cycled wireless communications, the method comprising:
transmitting data packets by a master module;
receiving the data packets by a slave module;
setting a flag signal in response to the data packets being detected and resetting the flag signal upon completion of the data packets;
generating a clock signal by a signal generator of the slave module, the clock signal having a period equal to a time interval of two data packets transmitted by the master module;
utilizing the clock signal by a slave timer of the slave module to control the slave module; and
calibrating the slave timer based on the flag signal.

12. The method of claim 11 , wherein utilizing the clock signal to control the slave module comprises utilizing the clock signal to wake the slave module.

13. The method of claim 11 , wherein utilizing the clock signal to control the slave module comprises utilizing the clock signal to cause the slave module to sleep.

14. The method according to claim 11 , wherein the slave module is implemented on a single integrated circuit.

15. The method according to claim 11 , wherein transmitting the data packets further comprises transmitting the data packets from the master module with a specific duty-cycle ratio and a specific time interval between the data packets.

16. The method according to claim 11 , wherein the master module includes a crystal oscillator, a microelectromechanical system (MEMS) based oscillator, or a bulk acoustic wave (BAW) based oscillator.

17. The method according to claim 11 , further comprising detecting the data packets via signal detection, energy detection, preamble detection, or synchronized frame detection.

18. The method according to claim 11 , wherein setting the flag signal comprises setting the flag signal to high in response to the data packets being detected and resetting the flag signal comprises resetting the flag signal to zero upon completion of the data packets, thereby generating the clock signal such that the period is equal to the time interval.

Assignees

• Stichting Imec Nederland

Inventors

• Ding Ming
• Liu Yao-Hong

Classifications

• Y02D30/70

  in wireless communication networks · CPC title

• H04L7/0012 Primary

  by comparing receiver clock with transmitter clock · CPC title

• H04W52/028

  switching on or off only a part of the equipment circuit blocks · CPC title

• H04B1/40 Primary

  Circuits · CPC title