Semiconductor devices with memory cells

Patent metadata

Field	Value
Publication number	US-11462552-B2
Application number	US-202117146439-A
Country	US
Kind code	B2
Filing date	Jan 11, 2021
Priority date	Jan 11, 2021
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

First claim

What is claimed is:

1. A semiconductor device comprising:
an isolation region on a substrate;
a first row of gates and diffusion blocks on the isolation region, wherein each gate is arranged between two diffusion blocks and comprises a dielectric layer conforming to sides and a bottom of a gate structure, and wherein the dielectric layer contacts the two diffusion blocks in the first row; and
a first diffusion structure and a second diffusion structure on the isolation region, the first and second diffusion structures extending along a length of the isolation region, wherein the first row of gates and diffusion blocks are arranged between the first diffusion structure and the second diffusion structure, and wherein the dielectric layer of each gate contacts the first diffusion structure and the second diffusion structure.

2. The device of claim 1 , wherein the first diffusion structure, the second diffusion structure, and each diffusion block in the first row include at least one doped region that is in contact with the dielectric layer of each gate in the first row.

3. The device of claim 1 , wherein the two diffusion blocks that contact the dielectric layer of each gate in the first row are connected to different conductive lines.

4. The device of claim 3 , further comprising:
a first source line connected to the first diffusion structure;
a second source line connected to a first of the two diffusion blocks in the first row;
a third source line connected to a second of the two diffusion blocks in the first row; and
a fourth source line connected to the second diffusion structure.

5. The device of claim 4 , wherein each gate in the first row is connected to a word line and being configured to receive a voltage to control an electrical characteristic of at least one of the diffusion structures and the diffusion blocks that is in contact with the dielectric layer of each gate.

6. The device of claim 3 , further comprising
a second row of gates and diffusion blocks located on the isolation region, wherein each gate is arranged between two diffusion blocks and comprises a dielectric layer conforming to sides and a bottom of a gate structure, and wherein the dielectric layer contacts the two diffusion blocks in the second row;
a third diffusion structure and a fourth diffusion structure on the isolation region and extending along the length of the isolation region, wherein the second row of gates and diffusion blocks are arranged between the third diffusion structure and the fourth diffusion structure, and wherein the dielectric layer of each gate in the second row contacts the third diffusion structure and the fourth diffusion structure; and
a conductive line that connects one of the gates in the first row and one of the gates in the second row.

7. The device of claim 6 , further comprising:
a first source line connected to the first diffusion structure;
a second source line connected to a first of the two diffusion blocks in the first row;
a third source line connected to a second of the two diffusion blocks in the first row;
a fourth source line connected to the second diffusion structure
a fifth source line connected to the third diffusion structure;
a sixth source line connected to a first of the two diffusion blocks in the second row;
a seventh source line connected to a second of the two diffusion blocks in the second row;
an eighth source line connected to the fourth diffusion structure; and
a word line connected to one of the gates in the first row and one of the gates in the second row.

8. The device of claim 7 , wherein the word line extends perpendicularly across the first row and the second row.

9. A semiconductor device comprising:
an isolation region on a substrate;
a gate on the isolation region, the gate comprises a dielectric layer conforming to sides and a bottom of a gate structure; and
two diffusion blocks and two diffusion structures on the isolation region, wherein the gate is arranged between the two diffusion structures and the two diffusion blocks, and wherein the dielectric layer contacts the diffusion structures and diffusion blocks.

10. The device of claim 8 , wherein the diffusion structures and diffusion blocks are connected to different conductive lines and the gate is configured to receive a voltage to control an electrical characteristic of at least one of the diffusion structures and diffusion blocks that contacts the dielectric layer of the gate.

11. The device of claim 9 , wherein the gate is connected to a word line and the diffusion structures and diffusion blocks are connected to different source lines.

12. The device of claim 9 , wherein the gate is connected to a source line and the diffusion structures and diffusion blocks are connected to different word lines.

13. The device of claim 8 , wherein each diffusion structure and each diffusion block include at least one doped region that is in contact with the dielectric layer of the gate.

14. The device of claim 8 , wherein the gate structure is peripherally enclosed by the dielectric layer.

15. The device of claim 14 , wherein the sides of the gate structure provides at least 4 facets.

16. The device of claim 14 , wherein the sides of the gate structure provides at least 4 edges.

17. The device of claim 14 , wherein the sides of the gate structure provides at least 2 facets and at least 2 edges.

18. The device of claim 14 , wherein the sides of the gate structure form a circumferential surface.

19. A method of forming a semiconductor device comprising:
forming an isolation region on a substrate;
forming a first row of gates and diffusion blocks on the isolation region, wherein each gate is formed between two diffusion blocks and comprises a dielectric layer that conforms to sides and a bottom of a gate structure, and wherein the dielectric layer contacts the two diffusion blocks in the first row; and
forming a first diffusion structure and a second diffusion structure on the isolation region, the first and second diffusion structures extending along a length of the isolation region, wherein the first row of gates and diffusion blocks are formed between the first diffusion structure and the second diffusion structure, and the dielectric layer of each gate contacts the first diffusion structure and the second diffusion structure.

20. The method of claim 19 , further comprising forming at least one doped region in the first diffusion structure, the second diffusion structure, and each diffusion block in the first row, wherein the doped region contacts the dielectric layer of each gate in the first row.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Loy Desmond Jia Jun
• Chang Wei
• Toh Eng Huat
• Tan Shyue Seng

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H01L45/122

  Electricity · mapped topic

• H01L45/1641

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic