Memory test method, storage medium and computer device

Patent metadata

Field	Value
Publication number	US-11462287-B2
Application number	US-202117433333-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Mar 27, 2020
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

The present disclosure provides a memory test method, a storage medium and a computer device. The memory test method comprises: obtaining a target test pattern that needs to be written into a plurality of chip interfaces, the plurality of chip interfaces being connected to a plurality of physical interfaces in a one-to-one correspondence; determining second information of the chip interfaces corresponding to first information of the physical interfaces, and using the first information and the second information as corresponding connection information; remapping the corresponding connection information to obtain mapped connection information; and determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces.

First claim

The invention claimed is:

1. A memory test method, comprising:
obtaining a target test pattern that needs to be written into a plurality of chip interfaces of a memory, the plurality of chip interfaces being connected to a plurality of physical interfaces in a one-to-one correspondence;
determining second information of the chip interfaces corresponding to first information of the physical interfaces, and using the first information and the second information as corresponding connection information;
remapping the corresponding connection information to obtain mapped connection information;
determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces; and
writing the initial test pattern into the physical interfaces for writing the target test pattern into the chip interfaces;
wherein the method is performed by a processor.

2. The memory test method according to claim 1 , wherein the determining second information of the chip interfaces corresponding to first information of the physical interfaces comprises:
consecutively numbering the plurality of chip interfaces, the numbers of the chip interfaces being all integers;
consecutively numbering the plurality of physical interfaces, the numbers of the physical interfaces being all integers; and
determining the number of the chip interface connected to the physical interface numbered as a first character, the number of the chip interface being a second character, to obtain a correspondence relationship between the first character and the second character as the corresponding connection information.

3. The memory test method according to claim 2 , wherein the determining the number of the chip interface connected to the physical interface numbered as a first character, the number of the chip interface being a second character, comprises:
writing a first reference pattern into the plurality of physical interfaces, the first reference pattern being directed to the physical interface numbered as the first character;
obtaining a second reference pattern output from the plurality of chip interfaces, the second reference pattern being obtained by transmitting the first reference pattern; and
determining the number of the chip interface to which the second reference pattern is directed, the number of the chip interface being the second character.

4. The memory test method according to claim 2 , wherein the remapping the corresponding connection information to obtain mapped connection information comprises:
rearranging, based on the corresponding connection information, the first character mapped to each of the second characters as a third character to generate third information, according to consecutive numbers of the plurality of chip interfaces; and
using the first information and the third information as mapped connection information.

5. The memory test method according to claim 4 , wherein the initial numbers of the chip interfaces are equal to initial numbers of the physical interfaces, and the determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces comprises:
representing the target test pattern in binary, and left-shifting a target number in the target test pattern corresponding to the physical interface numbered as the first character to obtain intermediate numbers, wherein the left-shifted number of digits is equal to a value obtained by subtracting the initial number from the third character corresponding to the first character in the mapped connection information; and
adding the intermediate numbers to obtain the initial test pattern that needs to be written into the physical interfaces.

6. The memory test method according to claim 2 , wherein the consecutively numbering the plurality of chip interfaces comprises:
consecutively numbering the plurality of chip interfaces starting from 0; and
the consecutively numbering the plurality of physical interfaces comprises:
consecutively numbering the plurality of physical interfaces starting from 0.

7. The memory test method according to claim 1 , wherein the target test pattern and the initial test pattern are both non-binary numbers, and the determining, according to the target test pattern and the mapped connection information, an initial test pattern that needs to be written into the physical interfaces comprises:
representing the target test pattern in binary; and
determining, according to the target test pattern represented in binary and the mapped connection information, an initial test pattern represented in binary that needs to be written into the physical interfaces.

8. The memory test method according to claim 7 , wherein the target test pattern and the initial test pattern are both hexadecimal numbers.

9. The memory test method according to claim 8 , after the determining, according to the target test pattern represented in binary and the mapped connection information, an initial test pattern represented in binary that needs to be written into the physical interfaces, further comprising:
converting the initial test pattern represented in binary into the initial test pattern represented in hexadecimal.

10. The memory test method according to claim 1 , wherein the memory used with the memory test method is a double data rate synchronous dynamic random access memory.

11. The memory test method according to claim 1 , wherein the target test pattern and the initial test pattern are both data patterns.

12. The memory test method according to claim 1 , wherein the target test pattern and the initial test pattern are both address patterns.

13. A non-transitory computer-readable storage medium having a computer program stored thereon that, when executed by the processor, implements steps of the method according to claim 1 .

14. A computer device, comprising a second memory, the processor, and a computer program stored on the memory and capable of being run on the processor, wherein the processor implements steps of the method according to claim 1 .

Assignees

• Changxin Memory Tech Inc

Inventors

• Long Guangteng
• He Hao
• Lu Dan
• Hu Bo

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G11C29/16 Primary

  using microprogrammed units, e.g. state machines · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/46

  Test trigger logic · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title