Semiconductor device and image recognition system

Patent metadata

Field	Value
Publication number	US-11461633-B2
Application number	US-201816035010-A
Country	US
Kind code	B2
Filing date	Jul 13, 2018
Priority date	Aug 25, 2017
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

A semiconductor device includes an image recognition device having a convolution arithmetic processing circuit. The convolution arithmetic processing circuit includes a coefficient register where coefficients of an integration coefficient table are set, a product calculation circuit that calculates products of an input image and the coefficients, a channel register where a channel number of the integration coefficient table is set, a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and a plurality of output registers that store a result of the cumulative addition arithmetic operation. The integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N×N. The product calculation circuit can calculate data of N×N all at once.

First claim

What is claimed is:

1. An image recognition system comprising:
an image recognition device configured to perform an image recognition using a convolutional neural network, the image recognition device including a convolution arithmetic processing circuit, an activation circuit, and a pooling circuit;
an integration coefficient table generation device configured to:
receive a plurality of input coefficient tables, the plurality of input coefficient tables being respectively associated with channel numbers, the plurality of input coefficient tables respectively having M×M coefficients as their elements for a convolutional arithmetic operation; and
generate an integration coefficient table that has N×N coefficients as its elements by integrating the plurality of input coefficient tables, the integration coefficient table associating the N×N coefficients with N×N channel numbers, M and N each being an integer of 2 or more, M being a value smaller than N,
wherein the convolution arithmetic processing circuit includes a coefficient register and a channel register,
wherein the convolution arithmetic processing circuit is configured to read the N×N coefficients and the N×N channel numbers from the generated integration coefficient table and set their values in the coefficient register and the channel register, respectively;

wherein the convolution arithmetic processing circuit further includes:
a line buffer configured to receive input image data for a specified number of lines;
an input pattern register;
an input pattern generation circuit configured to change an arrangement of the input image data based on content of the input pattern register;
a product calculation circuit configured to calculate N×N element-wise products of the input image data output from the input pattern generation circuit and the coefficients set in the coefficient register;
a plurality of output registers;
an output control register configured to associate channel number with output register numbers, the output register numbers being the number of the plurality of output registers; and
a channel selection circuit configured to:
element-wisely associate the calculated N×N element-wise products with the N×N channel numbers set in the channel register;
cumulatively sum the calculated products with respect to each associated channel number; and
output, in accordance with the output control register, the cumulatively summed products to an output register associated with the channel number among the plurality of output registers,

wherein the product calculation circuit is configured to calculate data of N×N all at once to perform the image recognition.

2. The image recognition system according to claim 1 ,
wherein the channel selection circuit includes:
a cumulative addition circuit configured to add the products for each channel number; and
a cumulative addition register configured to hold an output of the cumulative addition circuit for each channel number, and

wherein the cumulative addition circuit is configured to perform the addition for each channel number in parallel.

3. The image recognition system according to claim 2 ,
wherein the channel selection circuit further includes a selector configured to output, with respect to each channel number, the output of the cumulative addition circuit to one of the output registers that is associated with the channel number.

4. The image recognition system according to claim 1 ,
wherein the line buffer is configured to receive the input image data of an input image of M×M, and
wherein the input pattern generation circuit is configured to change the arrangement of the input image data by repeating the input image data of the input image of M×M.

Assignees

• Renesas Electronics Corp

Inventors

• Nakamura Atsushi
• UTAGAWA Akira
• Matsuo Shigeru

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F17/153 Primary

  Multidimensional correlation or convolution · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06V10/94

  Hardware or software architectures specially adapted for image or video understanding · CPC title