Information processing apparatus and configuration method

Patent metadata

Field	Value
Publication number	US-11461524-B2
Application number	US-202017063849-A
Country	US
Kind code	B2
Filing date	Oct 6, 2020
Priority date	Nov 20, 2019
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

An information processing apparatus includes a central processing unit (CPU), a plurality of field-programmable gate arrays (FPGAs) connected to the CPU to communicate with the CPU, and a plurality of memories provided in a one-to-one relationship with the plurality of FPGAs. Each of the plurality of memories is configured to store configuration data of a corresponding one of the plurality of FPGAs. One of the plurality of FPGAs is configured to update the configuration data of each of the plurality of FPGAs stored in a corresponding one of the plurality of memories.

First claim

What is claimed is:

1. An information processing apparatus comprising:
a central processing unit (CPU);
a plurality of field-programmable gate arrays (FPGAs) connected to the CPU to communicate with the CPU; and
a plurality of memories provided in a one-to-one relationship with the plurality of FPGAs,
each of the plurality of memories to store configuration data of a corresponding one of the plurality of FPGAs,
one of the plurality of FPGAs being configured to update the configuration data of each of the plurality of FPGAs stored in a corresponding one of the plurality of memories.

2. The information processing apparatus according to claim 1 , further comprising a switcher configured to switch a connection destination of the one of the plurality of FPGAs between the plurality of memories,
wherein the one of the plurality of FPGAs is configured to control the switcher to switch the connection destination of the one of the plurality of FPGAs to one of the plurality of memories, the one of the plurality of memories corresponding to another one of the plurality of FPGAs other than the one of the plurality of FPGAs, to update the configuration data of said another one of the plurality of FPGAs stored in the one of the plurality of memories.

3. The information processing apparatus according to claim 2 , further comprising a plurality of serial buses connecting the plurality of FPGAs with the plurality of memories in the one-to-one relationship,
wherein the one of the plurality of FPGAs is configured to switch a connection destination of at least one of the plurality of serial buses, the at least one of the plurality of serial buses being connected to the one of the plurality of FPGAs, to at least another one of the plurality of serial buses other than the at least one of the plurality of serial buses, the at least another one of the plurality of serial buses being connected to the one of the plurality of memories, to switch the connection destination of the one of the plurality of FPGAs to the one of the plurality of memories.

4. The information processing apparatus according to claim 1 ,
wherein one of the plurality of memories corresponding to the one of the plurality of FPGAs is configured to store update configuration data that is used for updating, and
wherein the one of the plurality of FPGAs is configured to update the configuration data of each of the plurality of FPGAs stored in a corresponding one of the plurality of memories, in response to the update configuration data stored in the one of the plurality of memories being written to the one of the plurality of FPGAs.

5. The information processing apparatus according to claim 1 , wherein:
others of the plurality of FPGAs not including the one of the plurality of FPGAs not being configured to update the configuration data of each of the plurality of FPGAs.

6. A configuration method for an information processing apparatus, the information processing apparatus including a central processing unit (CPU), a plurality of field-programmable gate arrays (FPGAs) connected to the CPU to communicate with the CPU, and a plurality of memories provided in a one-to-one relationship with the plurality of FPGAs, each of the plurality of memories to store configuration data of a corresponding one of the plurality of FPGAs,
the configuration method comprising updating, with one of the plurality of FPGAs, the configuration data of each of the plurality of FPGAs stored in a corresponding one of the plurality of memories.

7. The method according to claim 6 , further comprising:
switching a connection destination of the one of the plurality of FPGAs between the plurality of memories,
wherein the one of the plurality of FPGAs performs controlling the switching to switch the connection destination of the one of the plurality of FPGAs to one of the plurality of memories, the one of the plurality of memories corresponding to another one of the plurality of FPGAs other than the one of the plurality of FPGAs, to update the configuration data of said another one of the plurality of FPGAs stored in the one of the plurality of memories.

8. The method according to claim 7 , wherein the information processing apparatus further includes a plurality of serial buses configured to connect the plurality of FPGAs with the plurality of memories in the one-to-one relationship,
wherein the one of the plurality of FPGAs further performs switching a connection destination of at least one of the plurality of serial buses, the at least one of the plurality of serial buses being connected to the one of the plurality of FPGAs, to at least another one of the plurality of serial buses other than the at least one of the plurality of serial buses, the at least another one of the plurality of serial buses being connected to the one of the plurality of memories, to switch the connection destination of the one of the plurality of FPGAs to the one of the plurality of memories.

9. The method according to claim 6 , wherein:
wherein one of the plurality of memories corresponding to the one of the plurality of FPGAs performs storing update configuration data that is used for updating, and
wherein the one of the plurality of FPGAs performs updating the configuration data of each of the plurality of FPGAs stored in a corresponding one of the plurality of memories, in response to the update configuration data stored in the one of the plurality of memories being written to the one of the plurality of FPGAs.

10. The method according to claim 6 , wherein:
others of the plurality of FPGAs not including the one of the plurality of FPGAs not updating the configuration data of each of the plurality of FPGAs.

Assignees

• Ricoh Co Ltd

Inventors

• Shibata Takayuki
• Sakurada Yuichi
• Ishii Tatsuya

Classifications

• H03K19/17736 Primary

  Structural details of routing resources · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F15/7871

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title