Array substrate, light control panel, and display device

Patent metadata

Field	Value
Publication number	US-11460743-B2
Application number	US-202017288188-A
Country	US
Kind code	B2
Filing date	Aug 19, 2020
Priority date	Aug 23, 2019
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

An array substrate, a light control panel and a display device are provided. The array substrate includes a plurality of gate lines respectively extending along a first direction, a plurality of data lines respectively extending along a second direction intersected with the first direction, and a plurality of light control pixel units. Each of the plurality of gate lines includes a plurality of grid parts arranged side by side along the first direction and connected in sequence, and each of the plurality of grid parts includes a grid line and an opening area surrounded by the grid line.

First claim

What is claimed is:

1. An array substrate, comprising a plurality of gate lines respectively extending along a first direction, a plurality of data lines respectively extending along a second direction intersected with the first direction, and a plurality of light control pixel units,
wherein each of the plurality of gate lines comprises a plurality of grid parts arranged side by side along the first direction and connected in sequence, and each of the plurality of grid parts comprises a grid line and an opening area surrounded by the grid line, wherein the opening area surrounded by each of the plurality of grid parts is partly overlapped with one or two of the plurality of light control pixel units in a direction perpendicular to the array substrate.

2. The array substrate according to claim 1 , wherein the grid line of each of the plurality of grid parts comprises a first polygonal-line shaped trace and a second polygonal-line shaped trace;
a starting point of the first polygonal-line shaped trace is connected with a starting point of the second polygonal-line shaped trace;
an ending point of the first polygonal-line shaped trace is connected with an ending point of the second polygonal-line shaped trace; and
a vertex of the first polygonal-line shaped trace and a vertex of the second polygonal-line shaped trace are spaced apart in the second direction.

3. The array substrate according to claim 2 , wherein the first polygonal-line shaped trace comprises a first line segment and a second line segment which are sequentially connected, and a connection point between the first line segment and the second line segment is the vertex of the first polygonal-line shaped trace;
the second polygonal-line shaped trace comprises a third line segment and a fourth line segment which are sequentially connected, and a connection point between the third line segment and the fourth line segment is the vertex of the second polygonal-line shaped trace; and
an absolute value of an acute angle between the first line segment and the first direction, an absolute value of an acute angle between the second line segment and the first direction, an absolute value of an acute angle between the third line segment and the first direction, and an absolute value of an acute angle between the fourth line segment and the first direction are between 38 degrees and 55 degrees.

4. The array substrate according to claim 3 , wherein the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the absolute value of the acute angle between the third line segment and the first direction, and the absolute value of the acute angle between the fourth line segment and the first direction are between 42 degrees and 48 degrees.

5. The array substrate according to claim 3 , wherein the first polygonal-line shaped trace and the second polygonal-line shaped trace are symmetrical with respect to a connecting line between the starting point of the first polygonal-line shaped trace and the ending point of the first polygonal-line shaped trace.

6. The array substrate according to claim 3 , wherein the first line segment and the second line segment are symmetrical with respect to a connecting line between the vertex of the first polygonal-line shaped trace and the vertex of the second polygonal-line shaped trace; and
the third line segment and the fourth line segment are symmetrical with respect to the connecting line between the vertex of the first polygonal-line shaped trace and the vertex of the second polygonal-line shaped trace.

7. The array substrate according to claim 1 , wherein each of the plurality of data lines has two overlapping positions with the grid line of one corresponding grid part in a direction perpendicular to the array substrate, or each of the plurality of data lines is overlapped with a connecting position between two adjacent grid parts in the direction perpendicular to the array substrate.

8. The array substrate according to claim 7 , further comprising common electrode lines extending along the second direction,
wherein each of the common electrode lines is overlapped with the connecting position between the two adjacent grid parts in the direction perpendicular to the array substrate, or
each of the common electrode lines has two overlapping positions with the grid line of one corresponding grid part in the direction perpendicular to the array substrate.

9. The array substrate according to claim 2 , wherein a boundary trace of each of the plurality of light control pixel units is formed by corresponding data lines and the first polygonal-line shaped traces of the grid parts of corresponding gate lines; and
the second polygonal-line shaped trace of the grid part of each of the plurality of gate lines passes through an interior of a corresponding light control pixel unit.

10. The array substrate according to claim 2 , further comprising common electrode lines extending along the second direction, wherein
each of the common electrode lines is overlapped with a connecting position between two adjacent grid parts in a direction perpendicular to the array substrate;
a boundary trace of each of the plurality of light control pixel units is formed by corresponding common electrode lines and the first polygonal-line shaped traces of the grid parts of corresponding gate lines; and
the second polygonal-line shaped trace of the grid part of each of the plurality of gate lines passes through an interior of a corresponding light control pixel unit.

11. The array substrate according to claim 2 , wherein each of the plurality of light control pixel units further comprises a switching element and a pixel electrode;
the switching element comprises a gate electrode, a source electrode and a drain electrode,
the gate electrode of the switching element is electrically connected with a corresponding second polygonal-line shaped trace, and one of the source electrode and the drain electrode of the switching element is electrically connected with the pixel electrode; and
the switching element and the second polygonal-line shaped trace have the same amount as each other.

12. The array substrate according to claim 2 , wherein a width of the first polygonal-line shaped trace and a width of the second polygonal-line shaped trace both are between 9 microns and 11 microns.

13. The array substrate according to claim 1 , wherein the grid line of each of the plurality of grid parts comprises a first polygonal-line shaped trace and a second polygonal-line shaped trace;
a starting point of the first polygonal-line shaped trace is connected with a starting point of the second polygonal-line shaped trace; an ending point of the first polygonal-line shaped trace is connected with an ending point of the second polygonal-line shaped trace;
a vertex of the first polygonal-line shaped trace and a vertex of the second polygonal-line shaped trace are spaced apart in the second direction;
the first polygonal-line shaped trace comprises a first line segment and a second line segment which are sequentially connected, and a connection point between the first line segment and the second line segment is the vertex of the first polygonal-line shaped trace;
the second polygonal-line shaped trace comprises a third line segment and a fourth line segment which are sequentially connected, and a connection point between the third line segment and the fourth line segment is the vertex of the second polygonal-line shaped trace;
an absolute value of an acute angle between the first line segment and

Assignees

• Wuhan Boe Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Guo Yuanhui
• Gao Yujie
• Guo Wei
• Guo Kun
• Liao Yanping

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/133611

  including means for improving the brightness uniformity · CPC title

• G02F1/133606

  including a specially adapted diffusing, scattering or light controlling members · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title