Techniques and device structures based upon directional dielectric deposition and bottom-up fill

Patent metadata

Field	Value
Publication number	US-11459652-B2
Application number	US-202017072143-A
Country	US
Kind code	B2
Filing date	Oct 16, 2020
Priority date	Oct 16, 2020
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.

First claim

What is claimed is:

1. A method, comprising:
providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls;
providing a seed layer over the plurality of device structures;
forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base; and
forming a fill material within one or more trenches defined by the plurality of device structures.

2. The method of claim 1 , further comprising forming the fill material using a bulk atomic layer deposition process or a bulk chemical vapor deposition process.

3. The method of claim 1 , wherein the fill material is formed just along a lower portion of the first and second sidewalls.

4. The method of claim 1 , wherein the fill material is not formed over the dielectric layer.

5. The method of claim 1 , wherein forming the dielectric layer comprises depositing a dielectric material using a plasma enhanced chemical vapor deposition process.

6. The method of claim 1 , further comprising etching the plurality of device structures to remove the dielectric layer from the top surface of each of the plurality of device structures.

7. The method of claim 1 , further comprising depositing a second fill material over the fill material.

8. The method of claim 7 , further comprising planarizing the second fill material and the plurality of device structures to remove the seed layer from the top surface of each of the plurality of device structures.

9. The method of claim 1 , further comprising:
etching the plurality of device structures to remove the dielectric layer and the seed layer from the top surface of each of the plurality of device structures; and
forming a second fill material over the fill material.

10. A method of forming a semiconductor device, comprising:
providing a plurality of device structures extending vertically from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls;
providing a seed layer over the first sidewall, the second sidewall, and the top surface;
forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled dielectric material deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base; and
depositing a fill material within one or more trenches defined by the plurality of device structures, wherein the fill material is inhibited from being formed along the dielectric layer.

11. The method of claim 10 , further comprising depositing the fill material using a bulk atomic layer deposition process or a bulk chemical vapor deposition process.

12. The method of claim 10 , wherein the fill material is formed just along a lower portion of the first and second sidewalls.

13. The method of claim 10 , further comprising forming the dielectric layer using a plasma enhanced chemical vapor deposition process.

14. The method of claim 10 , further comprising:
etching the plurality of device structures to remove the dielectric layer from the top surface of each of the plurality of device structures;
depositing a second fill material over the fill material; and
planarizing the second fill material and the plurality of device structures to remove the seed layer from the top surface of each of the plurality of device structures.

15. The method of claim 10 , further comprising:
etching the plurality of device structures to remove the dielectric layer and the seed layer from the top surface of each of the plurality of device structures; and
forming a second fill material over the fill material.

16. A method, comprising:
providing a semiconductor device including a plurality of device structures extending vertically from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls;
providing a seed layer over the plurality of device structures;
forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base; and
depositing a fill material over a portion of the seed layer extending between adjacent device structures of the plurality of device structures.

17. The method of claim 16 , further comprising depositing the fill material using a bulk atomic layer deposition process or a bulk chemical vapor deposition process, wherein the fill material is inhibited from forming along the dielectric layer.

18. The method of claim 16 , wherein the fill material is formed along just a lower portion of the first and second sidewalls.

19. The method of claim 16 , further comprising:
etching the semiconductor device to remove the dielectric layer from the top surface of each of the plurality of device structures;
depositing a second fill material over the fill material; and
planarizing the second fill material and the plurality of device structures to remove the seed layer from the top surface of each of the plurality of device structures.

20. The method of claim 16 , further comprising:
etching the plurality of device structures to remove the dielectric layer and the seed layer from the top surface of each of the plurality of device structures; and
forming a second fill material over the fill material.

Assignees

• Applied Materials Inc

Inventors

• Zeeshan M Arif
• Ma Tristan Y
• Chan Kelvin

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/432

  using selective deposition · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title