Microfluidic chips with one or more vias

Patent metadata

Field	Value
Publication number	US-11458474-B2
Application number	US-201815875940-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Jan 19, 2018
Publication date	Oct 4, 2022
Grant date	Oct 4, 2022

Abstract

Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

First claim

What is claimed is:

1. A method, comprising
defining a microfluidic element embedded within a first surface of a device layer, wherein the device layer comprises a layer of a microfluidic chip;
bonding a sealing layer to the first surface of the device layer,
wherein the sealing layer is directly connected to and adjacent a first surface of the microfluidic element, wherein the device layer is directly connected to and adjacent a second surface of the microfluidic element, wherein the second surface of the microfluidic element is opposite the first surface of the microfluidic element,
wherein the sealing layer is directed connected to and adjacent a first bus of a plurality of buses and wherein the device layer is directly connected to and adjacent the first bus of the plurality of buses, wherein the first bus is a channel that guides fluid through the microfluidic chip and wherein the first bus of the plurality of buses is immediately adjacent and connected to the microfluidic element; and

forming, after the bonding, vias within the device layer, wherein the vias extend entirely through the device layer from a second surface of the device layer through to the first surface of the device layer, wherein the second surface is located on a side of the device layer opposite the first surface, wherein a second bus of the plurality of buses is directly connected to the vias and directly connected to and adjacent the first surface of the device layer, and wherein the second bus is open to an environment outside of the microfluidic chip and fails to be encapsulated by the sealing layer and the device layer.

2. The method of claim 1 , wherein the forming the vias comprises etching through the device layer.

3. The method of claim 1 , further comprising thinning the device layer after the bonding and before the forming the vias.

4. The method of claim 3 , wherein the thinning comprises reducing a thickness of the device layer to a value greater than or equal to about 7 micrometers and less than or equal to about 500 micrometers.

5. The method of claim 1 , further comprising providing a sacrificial plug on the device layer and coplanar with the microfluidic element, wherein the sacrificial plug protects the microfluidic element from the forming the vias.

6. The method of claim 1 , wherein the forming the vias comprises forming greater than or equal to about 100 vias and less than or equal about 100,000 vias per square centimeter of a second surface.

Assignees

• IBM

Inventors

• Smith Joshua T
• Landers William Francis
• Winstel Kevin
• Wu Teresa Jacqueline

Classifications

• B01L3/502707 Primary

  characterised by the manufacture of the container or its components · CPC title

• G01N27/44791

  Microapparatus (sample containers with integrated microfluidic structures B01L3/5027) · CPC title

• B01L2200/12

  Specific details about manufacturing devices · CPC title

• B01L3/502715

  characterised by interfacing components, e.g. fluidic, electrical, optical or mechanical interfaces · CPC title

• B01D15/34 Primary

  Size-selective separation, e.g. size-exclusion chromatography; Gel filtration; Permeation · CPC title