Phase-locked loop circuit having linear voltage-domain time-to-digital converter with output subrange

Patent metadata

Field	Value
Publication number	US-11456750-B2
Application number	US-202117488339-A
Country	US
Kind code	B2
Filing date	Sep 29, 2021
Priority date	Nov 12, 2020
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

First claim

What is claimed is:

1. A phase-locked loop (PLL) circuit, comprising:
a time-to-digital converter (TDC), comprising:
a phase detector, for generating a charging current signal according to an input frequency signal and a feedback signal which is generated from a feedback circuit; and
a processing circuit, coupled to the phase detector, for limiting an analog voltage level, provided for an analog-to-digital converter of the processing circuit and corresponding to the charging current signal, in a voltage range according to a prediction signal to generate a digital output, the prediction signal being generated by a prediction circuit;

a loop filter, coupled to the TDC, for performing a low-pass filter operation according to the digital output;
a digital controlled oscillator (DCO), coupled to the loop filter, for generating a DCO frequency signal according to an output of the loop filter;
the feedback circuit, coupled to the DCO and the phase detector, for generating the feedback signal according to the DCO frequency signal;
a sigma-delta modulator (SDM), coupled to the feedback circuit, for generating a phase signal, which indicates accumulated phase shift information, to the prediction circuit according to information of the feedback circuit and fractional frequency information; and
the prediction circuit, coupled to the SDM, for generating the prediction signal according to the phase signal.

2. The PLL circuit of claim 1 , wherein the processing circuit is arranged for:
limiting the voltage level corresponding to the charging current signal in the voltage range by dynamically adjusting down the voltage level according to the prediction signal, so as to generate an adjusted voltage level;
generating a digital output with least significant bit (LSB) information according to the adjusted voltage level; and
combining the LSB information with most significant bit (MSB) information carried by the prediction signal to generate a combined digital output as the digital output.

3. The PLL circuit of claim 2 , wherein the adjusted voltage level is associated with a sawtooth-like waveform signal.

4. The PLL circuit of claim 1 , wherein the processing circuit comprises:
a plurality of adjustable delay units connected in series, for generating a plurality of control signals according to a charging start signal, the plurality of control signals being respectively used to make the voltage level be adjusted down;
wherein delay amounts of the plurality of adjustable delay units are determined by the prediction signal to determine timings of generating the plurality of control signals.

5. The PLL circuit of claim 4 , wherein the plurality of control signals are generated during a time interval specified by a signal edge of the input frequency signal and a signal edge of the feedback signal.

6. The PLL circuit of claim 5 , wherein the signal edge of the input frequency signal is a rising edge or a falling edge, and the signal edge of the feedback signal is another rising edge or another falling edge.

7. The PLL circuit of claim 5 , wherein the signal edge of the input frequency signal is the rising edge, and the signal edge of the feedback signal is another rising edge.

8. The PLL circuit of claim 2 , wherein the processing circuit is arranged for generating the LSB information by overlapping one bit information of a capacitor bank with another bit information of another capacitor bank.

9. A sub-range controlling circuit to be disposed between a charge pump and an analog-to-digital converter (ADC) in a phase-locked loop (PLL) circuit, comprising:
a plurality of capacitor banks each comprising:
a plurality of capacitor units each having a first terminal coupled to an output of the charge pump and coupled an input of the ADC and having a second terminal; and
a plurality of switch units each having a first terminal coupled to the second terminal of a corresponding capacitor unit and having a second terminal selectively coupled to one of a reference voltage and a ground level; and

a control logic circuit, coupled to the plurality of capacitor banks, for limiting a voltage level corresponding to the output of the charge pump in a voltage range by respectively controlling states of switch units in at least one capacitor bank to dynamically adjust down the voltage level for one time or multiple times to generate an adjusted voltage level for the ADC.

10. The sub-range controlling circuit of claim 9 , wherein the control logic circuit is arranged for controlling all switch units in each capacitor bank becoming connected to the reference level and disconnected from the ground level when charging of the charge pump starts.

11. The sub-range controlling circuit of claim 10 , wherein the control logic circuit is arranged for controlling switch units of a specific capacitor bank becoming connected to the ground level and disconnected from the reference level at a specific timing to adjust down the voltage level.

12. A method of a phase-locked loop (PLL) circuit, comprising:
using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal which is generated from a feedback circuit;
limiting an analog voltage level, provided for an analog-to-digital converter of the processing circuit and corresponding to the charging current signal, in a voltage range according to a prediction signal to generate a digital output;
using a loop filter to perform a low-pass filter operation according to the digital output;
using a digital controlled oscillator (DCO) to generate a DCO frequency signal according to an output of the loop filter;
using the feedback circuit to generate the feedback signal according to the DCO frequency signal;
using a sigma-delta modulator (SDM) to generate a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and
generating the prediction signal according to the phase signal.

13. The method of claim 12 , wherein the limiting step comprises:
limiting the voltage level corresponding to the charging current signal in the voltage range by dynamically adjusting down the voltage level according to the prediction signal, so as to generate an adjusted voltage level;
generating a digital output with least significant bit (LSB) information according to the adjusted voltage level; and
combining the LSB information with most significant bit (MSB) information carried by the prediction signal to generate a combined digital output as the digital output.

14. The method of claim 13 , wherein the adjusted voltage level is associated with a sawtooth-like waveform signal.

15. The method of claim 12 , wherein the step comprises:
using a plurality of adjustable delay units connected in series to generate a plurality of control signals according to a charging start signal, the plurality of control signals being respectively used to make the voltage level be adjusted down;
wherein delay amounts of the plurality of adjustable delay units are determined by the prediction signal to determine timings of generating the plurality of control signals.

16. The method of claim 15 , wherein the plurality of control signals are generated during a time interval specified by a signal edge of the input frequency signal and a signal edge of the feedback signal.

17. The method of claim 16 , wherein the signal edge of the input frequency signal is a rising edge or a falling edge, and the signal edge of the feedback signal is another rising edge or a

Assignees

• Mediatek Inc

Inventors

• Lin Ang-Sheng
• Chang Chun-Wei
• Chueh Tzu-Chan

Classifications

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/0895

  Details of the current generators (H03L7/0893 takes precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title