Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11456218-B2
Application number	US-202017004173-A
Country	US
Kind code	B2
Filing date	Aug 27, 2020
Priority date	Jun 3, 2020
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming, on a substrate, a plurality of stacks and an isolation structure among the plurality of stacks, wherein each stack comprises a first doping layer, a second doping layer, and, a channel layer located between the first doping layer and the second doping layer;
for each stack,
etching the channel layer laterally from at least one sidewall of said stack, to form a cavity located between the first doping layer and the second doping layer, and
forming a gate dielectric layer and a gate layer in the cavity;
wherein a first sidewall of said stack is contact with the isolation structure, the at least one sidewall does not comprise the first sidewall, and a part of the channel layer remains at the first sidewall of said stack after the etching.

2. The method according to claim 1 , wherein forming the plurality of multiple stacks and the isolation structure among the plurality of stacks on the substrate comprises:
forming, on the substrate, a first doping material layer, a second doping layer material, and a channel material layer located between the first doping material layer and the second doping material layer;
etching the first doping material layer, the channel material layer, and the second doping material layer, to form a first trench; and
forming the isolation structure in the first trench.

3. The method according to claim 2 , wherein etching the channel layer laterally comprises:
etching the first doping material layer, the channel material layer and the second doping material layer, to form a second trench, wherein the second trench exposes the at least one sidewall of said stack; and
etching the channel layer laterally via the second trench.

4. The method according to claim 3 , wherein after forming the gate dielectric layer and the gate layer in the cavity, the method further comprises:
filling the second trench with a dielectric material.

5. The method according to claim 1 , wherein forming the plurality of multiple stacks and the isolation structure among the plurality of stacks on the substrate comprises:
forming a dielectric layer on the substrate;
forming, in the dielectric layer, multiple through holes that run vertically through the dielectric layer; and
forming a stack in each through hole;
wherein the dielectric layer serves as the isolation structure among the plurality of stacks, the plurality of stacks comprises at least a first stack and a second stack, and the first stack and the second stack are different in material.

6. The method according to claim 5 , wherein etching the channel layer laterally comprises:
etching the dielectric layer to form a third trench, wherein the third trench exposes the at least one sidewall of said stack; and
etching the channel layer laterally via the third trench.

7. The method according to claim 6 , wherein after forming the gate dielectric layer and the gate layer in the cavity, the method further comprises:
filling the third trench with a dielectric material, wherein the dielectric material corresponds to said stack.

8. The method according to claim 3 , wherein:
the second trench is formed and another isolation structure is formed in the second trench, before the first trench is formed; and
the another isolation structure is removed from the second trench, after forming the isolation structure in the first trench.

9. The method according to claim 3 , wherein
the second trench divides the first doping material layer, the channel material layer, and the second doping material layer into a plurality of separate structures; and
each of the plurality of separate structures is divided into a plurality of portions by the first trench.

10. The method according to claim 9 , wherein one of the plurality of separate structures is divided into the plurality of portions by a plurality of sub-trenches of the first trench, wherein the plurality of sub-trenches intersects with each other.

11. The method according to claim 1 , wherein etching the channel layer laterally comprises:
performing a plurality of oxidation-removal processes;
wherein each of the plurality of oxidation-removal process comprises:
oxidizing the channel layer, to form an oxide layer on an exposed surface of the channel layer; and
removing the oxide layer.

12. The method according to claim 1 , wherein for each stack, the first doping layer, the channel layer and the second doping layer are made of:
SiGe, Si, SiGe, respectively;
Si, SiGe, Si, respectively; or
Ge, GeSn, Ge, respectively.

13. The method according to claim 1 , wherein a buffer layer is formed between the substrate and the plurality of stacks.

14. The method according to claim 1 , wherein:
an intrinsic layer corresponding to a material of the first doping layer is formed between the first doping layer and the channel layer, and
an intrinsic layer corresponding to a material of the second doping layer is formed between the channel layer and the second doping layer.

15. The method according to claim 1 , wherein:
in a case that the channel layers in the plurality of stacks are made of a same material, the isolation structure comprises a strain material layer, and the strain material layer is configured to provide compressive stress or tensile stress for the channel layer of each stack; and
in a case that the channel layers in the plurality of stacks are made of a plurality of materials, the isolation structure comprises a plurality of strain material layers, and the plurality of strain layers are configured to provide compressive stress or tensile stress for the plurality of materials, respectively.

16. The method according to claim 1 , wherein forming the gate dielectric layer and the gate layer in the cavity comprises:
depositing the gate dielectric layer and the gate layer, and
removing the gate dielectric layer and the gate layer that are located outside the cavity.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Wang Guilei
• Radamson Henry H
• Kong Zhenzhen
• Li Junjie
• Liu Jinbiao
• Li Junfeng
• Yin Huaxiang

Classifications

• H01L21/823885

  Electricity · mapped topic

• H01L21/823878

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L21/823487 Primary

  Electricity · mapped topic