Substrate evaluation chip and substrate evaluation device

Patent metadata

Field	Value
Publication number	US-11454601-B2
Application number	US-202016998395-A
Country	US
Kind code	B2
Filing date	Aug 20, 2020
Priority date	Feb 22, 2018
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

A substrate evaluation chip is used to perform a test for evaluating a thermal characteristic of a mounting substrate that is mountable a power semiconductor. The substrate evaluation chip includes an insulating substrate bonded with the mounting substrate, and a heating pattern that is formed on a surface of the insulating substrate by a metallic film and is arranged by having a predetermined shape that is optimized to beat the insulating substrate more uniformly. The insulating substrate is a substrate in which an insulating film is formed on a surface of a single crystal substrate having a thermal conductivity of 250 [W/mK] or more.

First claim

What is claimed is:

1. A substrate evaluation chip used to perform a test for evaluating a thermal characteristic of a mounting substrate on which a power semiconductor is mountable, the substrate evaluation chip comprising:
an insulating substrate bonded with the mounting substrate; and
a heating pattern that is formed on a surface of the insulating substrate by a metallic film and is arranged by having a predetermined shape that is optimized to heat the insulating substrate more uniformly, wherein
the insulating substrate is a substrate in which an insulating film is formed on a surface of a single crystal substrate having a thermal conductivity of 250 W/mK or more.

2. The substrate evaluation chip according to claim 1 , further comprising:
a temperature measurement pattern that is formed on the surface of the insulating substrate by a metallic film and is configured to measure a temperature of the insulating substrate heated by the heating pattern.

3. The substrate evaluation chip according to claim 1 , wherein
the insulating substrate is a substrate in which the insulating film is formed on a surface of an SiC-based single crystal substrate.

4. The substrate evaluation chip according to claim 1 , wherein
the mounting substrate is a ceramic wiring board.

5. A substrate evaluation device used to perform a test for evaluating a thermal characteristic of a mounting substrate on which a power semiconductor is mountable in a state in which a substrate evaluation chip is mounted on a surface of the mounting substrate, the substrate evaluation device comprising:
the substrate evaluation chip comprising an insulating substrate bonded with the mounting substrate, a heating pattern that is formed on a surface of the insulating substrate by a metallic film and is arranged by having a predetermined shape that is optimized to heat the insulating substrate more uniformly, a temperature measurement pattern that is formed on the surface of the insulating substrate by a metallic film and is configured to measure a temperature of the insulating substrate heated by the heating pattern, a first electrode pad connected to one end of the heating pattern on the surface of the insulating substrate and formed by a metallic film, a second electrode pad connected to another end of the heating pattern on the surface of the insulating substrate and formed by a metallic film, a third electrode pad connected to one end of the temperature measurement pattern on the surface of the insulating substrate and formed by a metallic film, and a fourth electrode pad connected to another end of the temperature measurement pattern on the surface of the insulating substrate and formed by a metallic film;
the mounting substrate comprising a chip bonding pattern bonded with the substrate evaluation chip and a plurality of pad bonding patterns respectively connected with one of the first electrode pad, the second electrode pad, the third electrode pad, and the fourth electrode pad;
a cooling unit configured to cool the mounting substrate;
a load application unit comprising a plurality of terminal electrodes for pressing the mounting substrate against the cooling unit via the plurality of pad bonding patterns;
a heating unit configured to raise a temperature of the insulating substrate of the substrate evaluation chip by heating the heating pattern of the substrate evaluation chip via any terminal electrodes of the plurality of terminal electrodes; and
a measuring unit configured to measure the temperature of the insulating substrate by the temperature measurement pattern of the substrate evaluation chip via any terminal electrodes of the plurality of terminal electrodes, wherein
the thermal characteristic of the mounting substrate is evaluated based on a measurement result of the measuring unit.

6. The substrate evaluation device according to claim 5 , wherein
each of the plurality of terminal electrodes comprises a contact portion that contacts with respective pad bonding patterns of the mounting substrate, and the contact portion has a hemispherical shape.

7. The substrate evaluation device according to claim 5 , wherein
the plurality of terminal electrodes are commonly supported by an insulating support member; and
the insulating support member comprises a load detection unit configured to detect a load at a time of pressing the mounting substrate against the cooling unit, the load being applied by the load application unit.

8. The substrate evaluation device according to claim 5 , wherein
the insulating substrate is a substrate in which an insulating film is formed on a surface of a single crystal substrate having a thermal conductivity of 250 W/mK or more.

9. The substrate evaluation device according to claim 5 , wherein
the insulating substrate is a substrate in which an insulating film is formed on a surface of an SiC-based single crystal substrate.

Assignees

• Univ Osaka
• Yamato Scient Co Ltd

Inventors

• Suganuma Katsuaki
• Nagao Shijo
• Shimoyama Akio
• Kim Dongjin
• Takeshita Kazutaka
• Wakasugi Naoki

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title