Data transmission using delayed timing signals

Patent metadata

Field	Value
Publication number	US-11451218-B2
Application number	US-202016880694-A
Country	US
Kind code	B2
Filing date	May 21, 2020
Priority date	Nov 1, 2011
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

First claim

What is claimed is:

1. A dynamic random-access memory (DRAM) device comprising:
a memory circuit including a plurality of memory cells;
an interface circuit to receive a timing signal from a memory controller;
a plurality of receivers to receive data according to the timing signal received at the interface circuit, from the memory controller, the data for storage in the memory circuit; and
a circuit to compare the data and the timing signal and to output, to the memory controller, a signal indicative of a phase comparison of a phase of the timing signal and a phase of the data.

2. The DRAM device of claim 1 , wherein the data is a test pattern received during a calibration mode of the DRAM device, and the circuit comprises:
a delay circuit coupled to the interface circuit, the delay circuit to delay the phase of the timing signal by a delay to generate a delayed phase of the timing signal during the calibration mode;
a phase comparator to generate the signal indicative of the phase comparison based on a comparison of the delayed phase of the timing signal and the phase of the test pattern; and
a buffer circuit to transmit the signal indicative of the phase comparison.

3. The DRAM device of claim 2 , wherein the interface circuit receives from the memory controller an adjusted timing signal have an adjusted phase based on the signal indicative of the phase comparison output by the circuit.

4. The DRAM device of claim 1 , wherein the data is a test pattern received during a calibration mode of the DRAM device, and the circuit comprises:
a phase comparator to generate the signal indicative of the phase comparison based on a comparison of the phase of the timing signal and the phase of the test pattern during the calibration mode.

5. The DRAM device of claim 4 , wherein the interface circuit receives from the memory controller an adjusted timing signal having an adjusted phase based on the signal output by the circuit.

6. The DRAM device of claim 1 , wherein each of the plurality of receivers includes a plurality of flip flop circuits to sample the data for storage in the memory circuit.

7. The DRAM device of claim 1 , further comprising a timing signal path, wherein the interface circuit includes a plurality of buffers that buffer the timing signal received by the interface circuit, the buffered timing signal provided to the plurality of receivers via the timing signal path.

8. The DRAM device of claim 1 , wherein each of the plurality of receivers lack a replica circuit that delays the data for sampling.

9. A method of a dynamic random-access memory (DRAM) device comprising:
receiving a timing signal from a memory controller at an interface circuit;
sampling data in response to the timing signal received at the interface circuit, the data for storage in a memory circuit that includes a plurality of memory cells;
comparing the data and the timing signal; and
outputting a signal to the memory controller, the signal indicative of a phase comparison of a phase of the timing signal received at the interface circuit and a phase of the data.

10. The method of claim 9 , wherein the data is a test pattern received during a calibration mode of the DRAM device, the method further comprising:
delaying the phase of the timing signal by a delay to generate a delayed phase of the timing signal during the calibration mode of the DRAM device; and
wherein outputting the signal indicative of the phase comparison further comprises generating the signal indicative of the phase comparison based on a comparison of the delayed phase of the timing signal and the phase of the test pattern during the calibration mode.

11. The method of claim 10 , further comprising:
receiving from the memory controller an adjusted timing signal having an adjusted phase based on the signal indicative of the phase comparison.

12. The method of claim 9 , wherein the data is a test pattern received during a calibration mode of the DRAM device, and outputting the signal indicative of the phase comparison comprises:
generating the signal indicative of the phase comparison based on a comparison of the phase of the timing signal and the phase of the test pattern during the calibration mode of the DRAM device.

13. The method of claim 12 , further comprising:
receiving from the memory controller an adjusted timing signal having an adjusted phase based on the signal indicative of the phase comparison.

14. The method of claim 12 , wherein the data is sampled for storage in the memory circuit using a plurality of flip flop circuits included in the plurality of receivers.

15. The method of claim 9 , further comprising:
buffering the timing signal using a plurality of buffers included in the interface circuit, the buffered timing signal received by the plurality of receivers to sample the data.

16. A dynamic random-access memory (DRAM) device comprising:
a memory means;
means for receiving a timing signal from a memory controller;
means for receiving data, according to the timing signal received at the means for receiving the timing signal, from the memory controller, the data for storage in the memory means; and
means for comparing the data and the timing signal and outputting to the memory controller a signal indicative of a phase comparison of a phase of the timing signal and a phase of the data.

17. The DRAM device of claim 16 , wherein the data is a test pattern received during a calibration mode of the DRAM device, the DRAM device further comprising:
means for delaying the phase of the timing signal by a delay to generate a delayed phase of the timing signal during the calibration mode of the DRAM device; and
means for generating the signal indicative of the phase comparison based on a comparison of the delayed phase of the timing signal and the phase of the test pattern during the calibration mode; and
a means for transmitting the signal indicative of the phase comparison.

18. The DRAM device of claim 17 , wherein the means for receiving the timing signal receives from the memory controller receives an adjusted timing signal having an adjusted phase based on the signal indicative of the phase comparison.

19. The DRAM device of claim 16 , wherein the data is a test pattern received during a calibration mode of the DRAM device, and the means for outputting the signal indicative of the phase comparison comprises:
a means for generating the signal indicative of the phase comparison based on a comparison of the phase of the timing signal and then phase of the test pattern during the calibration mode of the DRAM device.

20. The DRAM device of claim 19 , wherein the means for receiving the timing signal receives from the memory controller receives an adjusted timing signal having an adjusted phase based on the signal indicative of the phase comparison.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely
• Leibowitz Brian
• Zerbe Jared

Classifications

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G06F13/4243

  with synchronous protocol · CPC title