Quantum dot devices with diodes for electrostatic discharge protection

Patent metadata

Field	Value
Publication number	US-11450765-B2
Application number	US-201816143676-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A quantum dot device is disclosed that includes a fin and a gate above the fin. The fin may extend away from a base and include a quantum well stack in which one or more quantum dots may be formed during operation of the quantum dot device. The gate may include a gate electrode material having a first portion and a second portion, where the first portion is above the quantum well stack and the second portion is a portion that is not above the quantum well stack and is separated from the base by an insulating material. The quantum dot device may further include a metal structure between the second portion of the gate electrode material and the base, forming a portion of a diode provided in series with the gate, which diode may provide at least some ESD protection for the quantum dot device.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a fin, extending away from a base, the fin comprising a quantum well stack;
a gate metal comprising a first portion and a second portion, wherein the first portion is above the quantum well stack, the second portion is electrically continuous with the first portion, and the second portion is separated from the base by an insulating material;
a semiconductor material having dopants at a dopant concentration of at least 5·10 19 dopants per cubic centimeter; and
a structure of one or more electrically conductive materials, the structure having a first end coupled to the semiconductor material and having a second end coupled to the second portion of the gate metal.

2. The quantum dot device according to claim 1 , wherein the first end is in direct contact with the semiconductor material and the second end is in direct contact with the second portion of the gate metal.

3. The quantum dot device according to claim 1 , wherein the semiconductor material is a portion of the base.

4. The quantum dot device according to claim 1 , wherein a depth of the semiconductor material is between 10 and 800 nanometers.

5. The quantum dot device according to claim 1 , wherein the dopants of the semiconductor material are N-type dopants.

6. The quantum dot device according to claim 1 , wherein the structure and the semiconductor material form a Schottky diode.

7. The quantum dot device according to claim 1 , wherein the structure has one or more sidewalls, at least portions of the one or more sidewalls being enclosed by the insulating material.

8. The quantum dot device according to claim 7 , wherein the one or more electrically conductive materials of the structure are in an opening in the insulating material.

9. The quantum dot device according to claim 1 , wherein the one or more electrically conductive materials of the structure includes one or more of molybdenum, platinum, chromium, tungsten, and a silicide.

10. The quantum dot device according to claim 1 , wherein an area of the structure in a cross-section in a plane parallel to the base is between 100 and 10,000 square nanometers.

11. The quantum dot device according to claim 1 , wherein a height of the structure is equal or greater than a height of the insulating material.

12. The quantum dot device according to claim 1 , further comprising a gate dielectric between the first portion of the gate metal and the quantum well stack, wherein the gate dielectric includes a high-k dielectric material.

13. The quantum dot device according to claim 1 , wherein the structure is an individual one of a plurality of structures between the second portion of the gate electrode and the base.

14. The quantum dot device according to claim 1 , further comprising one or more magnet lines.

15. A quantum dot device, comprising:
a fin, extending away from a base, the fin comprising a quantum well stack;
a gate metal; and
a diode between the gate metal and the base.

16. The quantum dot device according to claim 15 , wherein the diode is a Schottky diode.

17. The quantum dot device according to claim 15 , wherein:
the gate metal includes a first portion and a second portion,
the first portion is above the quantum well stack,
the second portion is not above the quantum well stack, and
the diode is between the second portion of the gate metal and the base.

18. The quantum dot device according to claim 15 , wherein the diode is in series with the gate metal.

19. The quantum dot device according to claim 15 , further comprising one or more magnet lines.

20. A method of manufacturing a quantum dot device, the method comprising:
forming a fin, extending away from a base, the fin comprising a quantum well stack;
providing an insulating material to enclose sidewalls of the fin;
forming an opening in the insulating material;
filling the opening with one or more electrically conductive materials;
forming a gate electrode line so that a first portion of the gate electrode is above the quantum well stack and a second portion of the gate electrode is electrically coupled to the one or more electrically conductive materials in the opening; and
doping a portion of a semiconductor material of the base to form a doped portion having a dopant concentration of at least 5·10 19 dopants per cubic centimeter,
wherein the one or more electrically conductive materials in the opening are in direct contact with the doped portion.

21. The method according to claim 20 , wherein a depth of the doped portion is between 450 and 550 nanometers.

22. The method according to claim 21 , wherein the one or more electrically conductive materials in the opening and the doped portion form a Schottky diode.

23. The method according to claim 21 , wherein the doped portion is formed prior to providing the insulating material.

24. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes a quantum dot device comprising:
a quantum well stack,
a gate above the quantum well stack,
a semiconductor material having dopants at a dopant concentration of at least 5·10 19 dopants per cubic centimeter, and
a structure comprising one or more metals, the structure having a first end in direct contact with the semiconductor material and having a second end in electrical contact with a portion of the gate; and

a non-quantum processing device, coupled to the quantum processing device, to control electrical signals applied to the gate.

25. The quantum computing device according to claim 24 , further comprising:
a cooling apparatus configured to maintain a temperature of the quantum processing device below 10 degrees Kelvin.

Assignees

• Intel Corp

Inventors

• George Hubert C
• Pillarisetty Ravi
• Lampert Lester
• Clarke James S
• Thomas Nicole K
• Caudillo Roman
• Singh Kanwaljit
• Michalak David J
• Roberts Jeanette M

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L23/5383

  Electricity · mapped topic

• H01L29/82

  Electricity · mapped topic