Display device

Patent metadata

Field	Value
Publication number	US-11450722-B2
Application number	US-202016871523-A
Country	US
Kind code	B2
Filing date	May 11, 2020
Priority date	Sep 9, 2019
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

A display device includes: a first semiconductor layer on a first buffer layer, and including a first active layer; a first gate insulating layer on the first semiconductor layer, and covering the first active layer; a first conductive layer on the first gate insulating layer, and including a first gate electrode; a second conductive layer on the first conductive layer, and including a first source/drain electrode; a first interlayer insulating layer on the first conductive layer; a second semiconductor layer on the first interlayer insulating layer, and including a second active layer; a second gate insulating layer on the second semiconductor layer, and covering the second active layer; and a third conductive layer on the second gate insulating layer, and including a second gate electrode and a second source/drain electrode. The first gate insulating layer and the second gate insulating layer include different insulating materials from each other.

First claim

What is claimed is:

1. A display device comprising:
a substrate;
a first buffer layer on the substrate;
a first semiconductor layer on the first buffer layer comprising a first active layer;
a first gate insulating layer on the first semiconductor layer and the first buffer layer, and covering the first active layer;
a first conductive layer on the first gate insulating layer comprising a first gate electrode;
a second conductive layer on the first conductive layer comprising a first source/drain electrode;
a first interlayer insulating layer on the first conductive layer;
a second semiconductor layer on the first interlayer insulating layer comprising a second active layer;
a second gate insulating layer on the second semiconductor layer covering the second active layer; and
a third conductive layer on the second gate insulating layer comprising a second gate electrode and a second source/drain electrode,
wherein the first gate insulating layer and the second gate insulating layer comprise different insulating materials from each other, and
wherein the first active layer and the second active layer overlap with each other.

2. The display device of claim 1 , wherein the first gate insulating layer comprises a single layer comprising silicon oxide, and
the second gate insulating layer comprises:
a first insulating layer comprising silicon oxide; and
a second insulating layer on the first insulating layer, and comprising silicon nitride or silicon oxynitride.

3. The display device of claim 2 , wherein the first insulating layer of the second gate insulating layer is in contact with the second active layer.

4. The display device of claim 3 , wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

5. The display device of claim 2 , wherein the first gate insulating layer comprises:
a third insulating layer comprising silicon oxide; and
a fourth insulating layer on the third insulating layer, and comprising silicon nitride or silicon oxynitride.

6. The display device of claim 5 , wherein the third insulating layer of the first gate insulating layer is in contact with the first active layer.

7. The display device of claim 5 , wherein a hydrogen content of the fourth insulating layer is lower than a hydrogen content of the second insulating layer.

8. The display device of claim 1 , wherein a width in one direction of a portion of the first active layer overlapping with the first gate electrode is greater than a width in the one direction of a portion of the second active layer overlapping with the second gate electrode.

9. The display device of claim 8 , wherein a thickness of the first gate insulating layer is greater than a thickness of the second gate insulating layer.

10. The display device of claim 8 , wherein a thickness of the first active layer is greater than a thickness of the second active layer.

11. The display device of claim 1 , further comprising a second buffer layer between the second active layer and the first interlayer insulating layer.

12. The display device of claim 11 , wherein the second semiconductor layer further comprises a third active layer on the second buffer layer, and the second gate insulating layer is on the third active layer.

13. The display device of claim 12 , wherein the third conductive layer further comprises a third gate electrode and a third source/drain electrode on the second gate insulating layer and overlapping with at least a portion of the third active layer.

14. The display device of claim 1 , further comprising a first protective layer between the second conductive layer and the first conductive layer, and between the second conductive layer and the first gate insulating layer,
wherein the second conductive layer is on the first protective layer, and further comprises one electrode of a first capacitor at least a portion of which overlaps with the first gate electrode.

15. The display device of claim 14 , further comprising:
a second interlayer insulating layer on the third conductive layer;
a data signal line on the second interlayer insulating layer;
a second protective layer on the data signal line; and
a conductive pattern on the second protective layer, and comprising at least a portion that overlaps with the data signal line.

16. A display device comprising:
a substrate;
a first buffer layer on the substrate;
a first semiconductor layer on the first buffer layer comprising a first active layer;
a first gate insulating layer on the first semiconductor layer and the first buffer layer covering the first active layer;
a first conductive layer on the first gate insulating layer comprising a first gate electrode;
a first interlayer insulating layer on the first conductive layer;
a second semiconductor layer on the first interlayer insulating layer comprising a second active layer;
a second gate insulating layer on the second semiconductor layer covering the second active layer; and
a second conductive layer on the second gate insulating layer comprising a second gate electrode,
wherein a thickness of the first gate insulating layer in a portion overlapping the first active layer is greater than a thickness of the second gate insulating layer in a portion overlapping the second active layer.

17. The display device of claim 16 , wherein a thickness of the first active layer is greater than a thickness of the second active layer.

18. The display device of claim 17 , wherein the first gate insulating layer comprises a single layer comprising silicon oxide, and
the second gate insulating layer comprises:
a first insulating layer comprising silicon oxide; and
a second insulating layer on the first insulating layer, and comprising silicon nitride.

19. The display device of claim 18 , wherein the second insulating layer of the second gate insulating layer comprises silicon oxynitride.

20. A display device comprising:
a substrate;
a driving transistor on the substrate comprising a first active layer, a first gate electrode, and a first source/drain electrode;
a first interlayer insulating layer on the driving transistor;
a first switching transistor on the first interlayer insulating layer comprising a second active layer, a second gate electrode, and a second source/drain electrode;
a first gate insulating layer between the first active layer and the first gate electrode; and
a second gate insulating layer between the second active layer and the second gate electrode,
wherein a width in one direction of a channel region of the first active layer is greater than a width in the one direction of a channel region of the second active layer, and
a dielectric constant of the first gate insulating layer is lower than a dielectric constant of the second gate insulating layer.

Assignees

• Samsung Display Co Ltd
• Samsung Display Co Lid

Inventors

• Kim Doo Na
• Kim Keun Woo
• Kang Tae Wook
• Lee Do Kyeong
• Lee Yong Su
• Chu Jae Hwan
• Kim Kwang Hyun
• Woo Yeoung Keol
• Chung Yung Bin

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H01L29/7869

  Electricity · mapped topic

• H01L27/3262 Primary

  Electricity · mapped topic