Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation

Patent metadata

Field	Value
Publication number	US-11450672-B2
Application number	US-202016859600-A
Country	US
Kind code	B2
Filing date	Apr 27, 2020
Priority date	Apr 27, 2020
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.

First claim

What is claimed is:

1. A memory device comprising:
a memory circuit including a plurality of groups of sub-arrays of Static Random Access Memory (SRAM) cells to store data; and
a plurality of Multiply-and-Accumulate units, each of the plurality of Multiply-and-Accumulate units to perform a multiply-and-accumulate operation on data stored in the memory circuit, the data to be routed on metal tracks in the memory circuit in the memory device between the plurality of Multiply-and-Accumulate units and the plurality of groups of sub-arrays of SRAM cells in both a vertical direction and a horizontal direction, the Multiply-and-Accumulate units placed in both the horizontal direction and the vertical direction to achieve a symmetric layout.

2. The memory device of claim 1 , wherein the plurality of groups of sub-arrays of SRAM cells includes a first group of sub-arrays of SRAM cells and a second group of sub-arrays of SRAM cells, a first data to be read from the first group of sub-arrays of SRAM cells while a second data is to be written to the second group of sub-arrays of SRAM cells.

3. The memory device of claim 2 , wherein each sub-array of SRAM cells includes a left sub-array and a right sub-array, the first data to be read from the left sub-array while the second data is to be written to the right sub-array.

4. The memory device of claim 3 , wherein input activations/weights are stored in the left sub-array and partial products/output activations are stored in the right sub-array.

5. The memory device of claim 3 , further comprising:
a network on chip (NOC) coupled to the plurality of Multiply-and-Accumulate units and the plurality of groups of sub-arrays of SRAM cells to allow the data to be routed between the plurality of Multiply-and-Accumulate units such that an output of a first MAC unit to be routed to an input of a second MAC unit.

6. The memory device of claim 5 , wherein the plurality of groups of sub-arrays of SRAM cells is 8 Megabytes, and a number of Multiply-and-Accumulate units is 256.

7. A method comprising:
storing data in a memory circuit in a memory device, the memory circuit including a plurality of groups of sub-arrays of Static Random Access Memory (SRAM) cells; and
performing, in a plurality of Multiply-and-Accumulate units in the memory device, a multiply-and-accumulate operation on data stored in the memory circuit, the data to be routed on metal tracks in the memory circuit in the memory device between the plurality of Multiply-and-Accumulate units and the plurality of groups of sub-arrays of SRAM cells in both a vertical direction and a horizontal direction, the Multiply-and-Accumulate units placed in both the horizontal direction and the vertical direction to achieve a symmetric layout.

8. The method of claim 7 , wherein the plurality of groups of sub-arrays of SRAM cells includes a first group of sub-arrays of SRAM cells and a second group of sub-arrays of SRAM cells, a first data to be read from the first group of sub-arrays of SRAM cells while a second data is to be written to the second group of sub-arrays of SRAM cells.

9. The method of claim 8 , wherein each sub-array of SRAM cells includes a left sub-array and a right sub-array, the first data to be read from the left sub-array while the second data is to be written to the right sub-array.

10. The method of claim 9 , wherein input activations/weights are stored in the left sub-array and partial products/output activations are stored in the right sub-array.

11. The method of claim 9 , further comprising:
routing the data between the plurality of Multiply-and-Accumulate units and the plurality of groups of sub-arrays of SRAM cells via a network on chip (NOC) coupled to the plurality of Multiply-and-Accumulate units and the plurality of groups of sub-arrays of SRAM cells such that an output of a first MAC unit to be routed to an input of a second MAC unit.

12. The method of claim 11 , wherein the plurality of groups of sub-arrays of SRAM cells is 8 Megabytes, and a number of Multiply-and-Accumulate units is 256.

13. A system comprising:
a memory device comprising:
a memory circuit including a plurality of groups of sub-arrays of Static Random Access Memory (SRAM) cells to store data; and
a plurality of Multiply-and-Accumulate units, each of the plurality of Multiply-and-Accumulate units to perform a multiply-and-accumulate operation on data stored in the memory circuit, the data to be routed on metal tracks in the memory circuit in the memory device between the plurality of Multiply-and-Accumulate units and the plurality of groups of sub-arrays of SRAM cells in both a vertical direction and a horizontal direction, the Multiply-and-Accumulate units placed in both the horizontal direction and the vertical direction to achieve a symmetric layout; and

a battery to power the system.

14. The system of claim 13 , wherein the plurality of groups of sub-arrays of SRAM cells includes a first group of sub-arrays of SRAM cells and a second group of sub-arrays of SRAM cells, a first data to be read from the first group of sub-arrays of SRAM cells while a second data is to be written to the second group of sub-arrays of SRAM cells.

15. The system of claim 14 , wherein each sub-array of SRAM cells includes a left sub-array and a right sub-array, the first data to be read from the left sub-array while the second data is to be written to the right sub-array.

16. The system of claim 15 , wherein input activations/weights are stored in the left sub-array and partial products/output activations are stored in the right sub-array.

17. The system of claim 15 , further comprising:
a network on chip (NOC) coupled to the plurality of Multiply-and-Accumulate units and the plurality of groups of sub-arrays of SRAM cells to allow the data to be routed between the plurality of Multiply-and-Accumulate units such that an output of a first MAC unit to be routed to an input of a second MAC unit.

18. The system of claim 17 , wherein the plurality of groups of sub-arrays of SRAM cells is 8 Megabytes, and a number of Multiply-and-Accumulate units is 256.

Assignees

• Intel Corp

Inventors

• Augustine Charles
• Paul Somnath
• Khellah Muhammad M
• Koren Chen

Classifications

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C11/412

  using field-effect transistors only · CPC title