Coupling of integrated circuits (ICS) through a passivation-defined contact pad

Patent metadata

Field	Value
Publication number	US-11450630-B2
Application number	US-202017081945-A
Country	US
Kind code	B2
Filing date	Oct 27, 2020
Priority date	Oct 27, 2020
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer.

First claim

What is claimed is:

1. A method, comprising:
depositing a first dielectric layer on an active side of a wafer;
forming conductive terminals on the active side of the wafer after depositing the first dielectric layer;
depositing a second dielectric layer on the active side of the wafer to passivate the conductive terminals;
patterning openings in the second dielectric layer to expose the conductive terminals, wherein the openings define contact pads for external components;
patterning trenches in the second dielectric layer between pairs of the openings in the second dielectric layer;
coupling the external components to the pairs of contact pads on the active side of the wafer; and
dividing the wafer into a plurality of chips after coupling the external components to the contact pads.

2. The method of claim 1 , wherein each external component of the external components are smaller in size than an outer dimension of each pair of contact pads of the pairs of contact pads to which each external component is coupled.

3. The method of claim 1 , further comprising depositing a conductive pad above the conductive terminals and coupled to the conductive terminals.

4. The method of claim 3 , wherein depositing a conductive pad comprises depositing an under bump metallization (UBM) pad.

5. The method of claim 1 , wherein depositing a first dielectric layer comprises depositing a first polymer-based dielectric layer, and wherein depositing a second dielectric layer comprises depositing a second polymer-based dielectric layer.

6. The method of claim 1 , further comprising depositing a plurality of balls on the active side of the wafer before dividing the wafer into a plurality of chips, wherein the plurality of balls are organized in a grid pattern, the grid pattern also comprising a plurality of depopulated ball locations, and wherein two pairs of the pairs of contact pads are arranged in the grid pattern for each of the plurality of depopulated ball locations.

7. The method of claim 1 , further comprising depositing a plurality of balls on the active side of the wafer before dividing the wafer into a plurality of chips, wherein the plurality of balls are organized in a grid pattern, the grid pattern also comprising a plurality of depopulated ball locations, and wherein a pair of the pairs of contact pads is arranged in the grid pattern for each of the plurality of depopulated ball locations.

8. The method of claim 1 , further comprising depositing a plurality of balls on the active side of the wafer before dividing the wafer into a plurality of chips, wherein the plurality of balls comprises a first plurality of balls corresponding to a first chip to be divided from the wafer and a second plurality of balls corresponding to a second chip to be divided from the wafer, wherein the contact pads are located on a portion of the wafer between the first plurality of balls and the second plurality of balls such that components corresponding to the first chip are located at a chip edge of the first chip when the first chip is divided from the wafer.

9. An apparatus, comprising:
a substrate;
a first dielectric layer on the substrate;
conductive terminals on the first dielectric layer;
a second dielectric layer on the first dielectric layer and on the conductive terminals;
openings in the second dielectric layer above the conductive terminals forming pairs of contact pads for external components, wherein trenches are included in the second dielectric layer between pairs of the openings; and
the external components coupled to the pairs of contact pads.

10. The apparatus of claim 9 , wherein each external component of the external components are smaller in size than an outer dimension of each pair of contact pads of the pairs of contact pads to which each external component is coupled.

11. The apparatus of claim 10 , further comprising a conductive pad above the conductive terminals and coupled to the conductive terminals.

12. The apparatus of claim 11 , wherein the conductive pad comprises an underbump metallization (UBM) pad.

13. The apparatus of claim 9 , wherein the first dielectric layer comprises a first polymer-based dielectric layer, and wherein the second dielectric layer comprises a second polymer-based dielectric layer.

14. The apparatus of claim 9 , further comprising a plurality of balls organized in a grid pattern, the grid pattern also comprising a plurality of depopulated ball locations, wherein two pairs of the pairs of contact pads are arranged in the grid pattern as a substitute for each of the plurality of depopulated ball locations.

15. The apparatus of claim 9 , further comprising a plurality of balls organized in a grid pattern, the grid pattern also comprising a plurality of depopulated ball locations, wherein a pair of the pairs of contact pads is arranged in the grid pattern as a substitute for two of the plurality of depopulated ball locations.

16. The apparatus of claim 9 , further comprising a plurality of balls, wherein the external components are located at a chip edge.

17. The apparatus of claim 9 , wherein the substrate comprises semiconductor transistors on an active side of the substrate, and wherein the external components are located on the active side of the substrate.

18. The apparatus of claim 9 , wherein the apparatus comprises a mixed signal device comprising analog signal processing components and digital signal processing components.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Healy Christopher

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/738

  between a chip and a stacked discrete passive device · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/07336

  Soldering or alloying · CPC title